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®
Intel XScale
Processor—Intel
3.7.2.3
Performance Monitor Control Register
The performance monitor control register (PMNC) is a coprocessor register that:
• Contains the PMU ID
• Extends CCNT counting by six more bits (cycles between counter rollover = 2
• Resets all counters to zero
• And enables the entire mechanism
Table 59
Table 59.
Performance Monitor Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: E and ID are 0, others unpredictable
Bits
31:24
23:4
3
2
1
0
3.7.2.4
Interrupt Enable Register
Each counter can generate an interrupt request when it overflows. INTEN enables
interrupt requesting for each counter.
Table 60.
Interrupt Enable Register (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: [4:0] = 0b00000, others unpredictable
Bits
31:5
4
3
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
shows the format of the PMNC register.
ID
Access
Read / Write Ignored
Read-unpredictable / Write-as-0
Read / Write
Read-unpredictable / Write
Read-unpredictable / Write
Read / Write
Access
Read-unpredictable / Write-as-0
Read / Write
Read / Write
Performance Monitor Identification (ID) -
IXP45X/IXP46X network processors = 0x14
Reserved
Clock Counter Divider (D) -
0 = CCNT counts every processor clock cycle
1 = CCNT counts every 64
Clock Counter Reset (C) -
0 = no action
1 = reset the clock counter to '0x0'
Performance Counter Reset (P) -
0 = no action
1 = reset all performance counters to '0x0'
Enable (E) -
0 = all counters are disabled
1 = all counters are enabled
Reserved
PMN3 Interrupt Enable (P3) -
0 = disable interrupt
1 = enable interrupt
PMN2 Interrupt Enable (P2) -
0 = disable interrupt
1 = enable interrupt
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
D C P E
Description
th
processor clock cycle
8
7
6
5
4
3
2
P
P
P
3
2
1
Description
Developer's Manual
38
)
1
0
1
0
P
C
0
159
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