3Execute Transaction - Intel IXP45X Developer's Manual

Intel
• If the EPS field indicates the endpoint is a high-speed endpoint, the Ping state field
is preserved by the host controller. The value of this field is not changed as a result
of the overlay.
• C-prog-mask field is set to zero (field from incoming qTD is ignored, as is the
current contents of the overlay area).
• Frame Tag field is set to zero (field from incoming qTD is ignored, as is the current
contents of the overlay area).
• NakCnt field in the overlay area is loaded from the RL field in the queue head's
Static Endpoint State.
• All other areas of the overlay are set by the incoming qTD.
The host controller exits this state when it has committed the write to the queue head.
9.14.10.3 Execute Transaction
The host controller enters this state from the Fetch Queue Head state only if the
Active bit in Status field of the queue head is set to a one.
On entry to this state, the host controller executes a few pre-operations, then checks
some pre-condition criteria before committing to executing a transaction for the queue
head.
The pre-operations performed and the pre-condition criteria depend on whether the
queue head is an interrupt endpoint. The host controller can determine that a queue
head is an interrupt queue head when the queue head's S-mask field contains a non-
zero value. It is the responsibility of software to ensure the S-mask field is
appropriately initialized based on the transfer type. There are other criteria that must
be met if the EPS field indicates that the endpoint is a low- or full-speed endpoint, see
Section 9.14.12.1, "Split Transactions for Asynchronous Transfers" on page 453
Section 9.14.12.2, "Split Transaction Interrupt" on page
• Interrupt Transfer Pre-condition Criteria
If the queue head is for an interrupt endpoint (e.g. non-zero S-mask field), then
the FRINDEX[2:0] field must identify a bit in the S-mask field that has a one in it.
For example, an S-mask value of 00100000b would evaluate to true only when
FRINDEX[2:0] is equal to 101b. If this condition is met then the host controller
considers this queue head for a transaction.
• Asynchronous Transfer Pre-operations and Pre-condition Criteria
If the queue head is not for an interrupt endpoint (e.g. a zero S-mask field), then
the host controller performs one pre-operation and then evaluates one pre-
condition criteria: The pre-operation is:
— Checks the Nak counter reload state
Nak Counter" on page
reload the Nak Counter field. The reload is performed at this time.
The pre-condition evaluated is:
— Whether or not the NakCnt field has been reloaded, the host controller checks
the value of the NakCnt field in the queue head. If NakCnt is non-zero, or if the
Reload Nak Counter field is zero, then the host controller considers this queue
head for a transaction.
• Transfer Type Independent Pre-operations
Regardless of the transfer type, the host controller always performs at least one
pre-operation and evaluates one pre-condition. The pre-operation is:
— A host controller internal transaction (down) counter qHTransactionCounter is
loaded from the queue head's Mult field. A host controller implementation is
allowed to ignore this for queue heads on the asynchronous list. It is
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
444
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
439). It may be necessary for the host controller to
455.
(Section 9.14.9, "Operational Model for
Order Number: 306262-004US
and
August 2006