Trimmed Version Of Ixp45X/Ixp46X Network Processors Memory Map; Expansion Bus Address Space; Chip Select Address Allocation - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
12.4.1.1

Expansion Bus Address Space

Table 219.

Trimmed Version of IXP45X/IXP46X network processors Memory Map

Start Address
0000_0000
0000_0000
4000_0000
4800_0000
5000_0000
6000_0000
As seen in
(0x00000000 to 0x0FFFFFFF) is overlapped with the DDRI SDRAM address space
(0x00000000 to 0x3FFFFFFF). The actual interface that is accessed when the
overlapped region is addressed is configurable based on the value of a configuration
register bit located in the Expansion bus controller.
When bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1, the
Expansion Bus accesses occupy the lowest 256-Mbytes of address space. When bit 31
of the Configuration Register 0 (EXP_CNFG0) is cleared to logic 0, the DDRI SDRAM
occupies the lowest 256-Mbytes of address.
On reset, bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1. This
setting is required to allow the boot memory to be accessed which is located at
hexadecimal address 0x00000000 in non-volatile storage on the Expansion Bus.
The first instruction execution of the Intel XScale processor is located at address
0x00000000. Once the boot sequence starts, the Intel XScale processor will switch bit
31 of the Configuration Register 0 (EXP_CNFG0) from logic 1 to logic 0, at an
appropriate time.
The information transfer from the flash to the DDRI SDRAM can be completed this way:
The configuration bit can be swapped to allow the DDRI SDRAM to have access at
address 0x00000000 and the remainder of the flash information can be retrieved
from the expansion bus address location 0x50000000 to 0x5FFFFFFF
12.4.1.2

Chip Select Address Allocation

The Expansion bus controller occupies 256 Mbytes of address space in the memory
map of the IXP45X/IXP46X network processors. The Expansion bus controller uses bits
27:0, from the AHB, to determine how to translate the AHB address to the Expansion
Bus Address. In order to maintain software compatibility with the IXP42X processors,
the address mapping depends on if there are 32 Mbyte devices programmed in any of
the EXP_TIMING_CS registers. Previous IXP42X processors did not support 32 Mbyte
devices and each chip select was allocated 16 Mbyte of addressing. With the addition of
support for 32 Mbyte devices, a new memory map is created so that each chip select is
allocated 32 Mbyte of addressing. If there are no 32 MByte devices programmed (i.e All
eight EXP_TIMING_CS registers bit 9 equal 0), the lower 24 bits of the AHB address are
translated to the lower 24 bits of the Expansion Bus address, EX_ADDR [23:0].
EX_ADDR[24] will always be zero. Bits 26:24 of the AHB are used to decode one of
eight chip-select regions implemented by the Expansion bus, each region being
16 Mbytes. Address bit 27 is not used and will currently alias each chip select region as
shown on the left side of
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
End Address
0FFF_FFFF
3FFF_FFFF
47FF_FFFF
4FFF_FFFF
5FFF_FFFF
63FF_FFFF
Table 219, on the AHB, the lowest 256 Mbytes of address space
Figure 124.
Intel
Size
256 Mbyte Expansion bus (Boot up)
1 Gbyte
128 Mbyte
128 Mbyte
256 Mbyte Expansion bus
64 Mbyte Queue manager
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Use
DDRI SDRAM
(Reserved)
PCI
Developer's Manual
653