Mcu Ddr Write Command To Next Command Timing Diagrams - Intel IXP45X Developer's Manual

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Memory Controller—Intel
Figure 112. MCU DDR Write Command to Next Command Timing Diagrams
t1
t0
m_clk
CMD W
t
WTRD
CMD W
t
WTCMD
non-reg,
BL=4, CAS=X
non-reg,
BL=4, CAS=4
Programming Examples:
Example A: non-reg, BL=4.
t =(1+(4/2)+2+0)=5
WRCMD
t =(1+(4/2)+1+0)=4
WTRD
Notes:
1. Nominal t assumed
DQSS
2. t = first pos. clock after last Data
WTR
3. Burst Writes cannot interrupt previous Writes
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
t3 t5 t7
t2 t4 t6
t
WR
0 1 2 3
0 1 2 3
t =3
WL
t =1
WL
(possible ONLY for
non-reg DIMMs)
Example B: reg, BL=4, t
t =(3+(4/2)+2+0)=7
WTCMD
t =(3+(4/2)+1+0)=6
WTRD
t9
t8 t10
Next allowed Read: reg, BL=4.
Next allowed Non-Read Command: reg, BL=4.
=2
t =1
WTR
t =1
WTR
t =2
WR
Write Duration Equations:
t =tWL + (BL/2) +t
WTCMD
t =t + (BL/2) +t
WTRD WL
=3
WL
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
+ t
WR REG
+ t
WTR REG
B4219-001
Developer's Manual
605