Utopia Receive Module - Intel IXP45X Developer's Manual

In cell-level single-PHY (SPHY) mode the physical interface indicates that it can accept
a cell by asserting the UTP_OP_FCI (also known as TX_FULL_N/TX_CLAV) signal. The
UTOPIA Level 2 Interface subsequently transmits a cell to the PHY at the same time
asserting UTP_OP_FCO (also known as TX_ENB_N).
For more timing diagrams and more details on operation in single-PHY (SPHY) mode of
operation, see the UTOPIA Level 2, Revision 1.0 Specification.
When using the UTOPIA Level 2 Interface in single-PHY (SPHY) mode the
UTP_OP_ADDR is driven with an address of all logic 1s and the UTP_IP_ADDR must be
driven with all logic 1s.
In octet-level single-PHY (SPHY) mode, the physical interface indicates to the UTOPIA
Level 2 Interface on the IXP45X/IXP46X network processors that the physical interface
can accept data by de-asserting UTP_OP_FCI (also known as TX_FULL_N/TX_CLAV)
signal. The UTOPIA Level 2 Interface subsequently transmits data to the PHY at the
same time, asserting UTP_OP_FCO (also known as TX_ENB_N).
When the physical interface de-asserts UTP_OP_FCI (also known as TX_FULL_N/
TX_CLAV), it indicates to the UTOPIA Level 2 Interface that the physical interface will
only accept four more bytes of data.
For more timing diagrams and details on the single-PHY (SPHY) mode of operation, see
the UTOPIA Level 2, Revision 1.0 Specification.
In addition to supporting data transmission and HEC generation, the Transmit Module
maintains some statistical values. The statistics that can be maintained are on a single
physical port address on a specified VPI/VCI address value. The 32-bit counters will
maintain the following counts:
• The number of cells transmitted
• The number of idle cells transmitted
The counters are not cleared when read by the Network Processor Engine core. The
Network Processor Engine core must perform an explicit write to the specified register
to clear the counter values. There is an overflow bit for each counter to indicate that
the count has "rolled-over." A mask-able interrupt mechanism is used to enable the
UTOPIA Level 2 coprocessor to flag to the Network Processor Engine core that the "roll
over" has occurred.
7.3

UTOPIA Receive Module

The functionality supported by the Receive Module is tightly coupled with the code
written on the Network Processor Engine core. This section details the full hardware
capabilities of the Receive Module contained within the UTOPIA Level 2 Coprocessor of
the IXP45X/IXP46X network processors. The module's user-accessible features are
described in the Intel
the features described in this section.
The UTOPIA Level 2 Receive interface receives ATM cells from one or more UTOPIA-
compliant physical devices.
In multiple-PHY (MPHY) mode, the UTOPIA Level 2 receive interface uses a round-robin
polling routine to poll the various physical interfaces using the five receive address lines
(UTP_IP_ADDR) to determine which physical interfaces are ready to send data. The
result of the polling is provided as status to the Network Processor Engine core. The
Receive Module is the entity within the UTOPIA coprocessor that implements this
functionality.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
272
® ®
Intel IXP45X and Intel
®
IXP400 Software Programmer's Guide and may be a subset of
IXP46X Product Line of Network Processors—UTOPIA Level 2
August 2006
Reference Number: 306262-004US