Gpio Input Register; Gpio Interrupt Status Register - Intel IXP45X Developer's Manual

®
GPIO Controller—Intel IXP45X and Intel
Register
Bits Name
31: 16 (Reserved) Reads back 0
1 = Output pin is tri-stated or input
15 OE15
0 = Output pin is driven
1 = Output pin is tri-stated or input
14:0 OE14:OE0
0 = Output pin is driven
15.5.3

GPIO Input Register

This is a read only register. This register contains the level of the I/O pin, either a '1' or
a '0'.
Register Name:
Physical Address:
Register Description:
Access: Read
3
1
(Reserved)
Register
Bits Name
31:1
(Reserved) Not used. Ignored on writes and driven logic '0' on reads.
6
Level of general-purpose inputs 15-0
15:0 IN_LEV 1 = 1 on GPIO
0 = 0 on GPIO
15.5.4

GPIO Interrupt Status Register

This register is used to store status of a GP input interpreted as an interrupt. GP input
interrupts can be configured as active high, active low, rising edge, falling edge, or
transitional depending upon the configuration of the GPIT[1:0]R register. A '1' read
from this register indicates a pending interrupt. Writing a '1' back to this register will
clear the interrupt provided the interrupting condition no longer exists. The interrupts
are all masked in the Interrupt Controller block.
Note: GPIO0 through GPIO12 can be used as an interrupt (see
Processor Interrupt Mapping" on page
August 2006
Reference Number: 306262-004US
®
IXP46X Product Line of Network Processors
Description
0xC8004008
This register is used to monitor input pins.
Description
Intel
GPOER
GPINR
Reset Hex Value:
1 1
6 5
GPINR
804)
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Reset Value Access
0x0
0
(as clock is driven
RW
out on this pin
during reset)
1 RW
0x00000000
8 7
IN_LEV
Reset
Access
Value
0x0 RO
0x0000 RO
Table 261, "Intel XScale®
Developer's Manual
RO
0
781