Master-Receiver Read From Slave-Transmitter - Intel IXP45X Developer's Manual

Intel
Table 279. Master Transactions (Sheet 2 of 2)
2
I C Master
Action
Read one byte
2
of I C Data from
the IDBR
Transmit
Acknowledge to
slave-
transmitter
Generate a
Repeated START
to chain I
transactions
Generate a
STOP
When the CPU needs to read data, the I
master-transmit mode to transmit the start address and immediately following the ACK
pulse transitions to master-receive mode to wait for the reception of the read data from
the slave device (see
during an I
through a repeated start or Data Chaining (see
wave forms of SDA and SCL for a complete data transfer.
Figure 198. Master-Receiver Read from Slave-Transmitter
START
Master to Slave
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
Mode of
Operation
Master-receive
only
Master-receive
only
Master-transmit
2
C
Master-receive
Master-transmit
Master-receive
Figure 198). It is also possible to have multiple transactions
2
C operation such as transitioning from master-receive to master-transmit
R/W#
Slave Address
First Byte Read
Slave to Master
2
• Data receive mode of I C master operation.
• Eight bits are read from the serial bus, collected in the shift register
then transferred to the IDBR after the Ack/Nack bit is read.
• The CPU reads the IDBR when the IDBR Receive Full bit is set and
the Transfer Byte bit is clear. If enabled, a IDBR Receive Full
Interrupt is signalled to the CPU.
• When the IDBR is read, if the Ack/Nack Status is clear (indicating
Ack), the IXP45X/IXP46X network processors will write the Ack/
Nack Control bit and set the Transfer Byte bit to initiate the next
byte read.
• If the Ack/Nack Status bit is set (indicating Nack), Transfer Byte bit
is clear, STOP bit in the ICR is set, and Unit Busy bit in the ISR is set,
then the last data byte has been read into the IDBR and the I
Interface Unit is sending the STOP.
• If the Ack/Nack Status bit is set (indicating Nack), Transfer Byte bit
is clear, but the STOP bit is clear, then the CPU has two options: 1.
set the START bit, write a new target address to the IDBR, and set
the Transfer Byte bit which will send a repeated start condition, 2.
set the Master Abort bit and leave the Transfer Byte clear which will
send a STOP only.
• As a master-receiver, the I
clock for the acknowledge pulse. The I
responsible for driving the SDA line during the Ack cycle.
• If the next data byte is to be the last transaction, the CPU will set
the Ack/Nack Control bit for Nack generation.
• See "I2C Acknowledge" on page
• If data chaining is desired, a repeated START condition is used
instead of a STOP condition.
• This occurs after the last data byte of a transaction has been written
to the bus.
• The CPU will write the next target slave address and the R/W# bit to
the IDBR, set the START bit, and set the Transfer Byte bit.
• See "Start and Stop Bus States" on page
• Generated after the CPU writes the last data byte on the bus.
• CPU generates a STOP condition by setting the STOP bit in the ICR.
• See "Start and Stop Bus States" on page
2
C unit transitions from slave-receive mode to
Figure
Data
ACK
1 Byte
Default
Slave-Receive
Mode
Definition
2
C Bus Interface Unit will generate the
2
C Bus Interface Unit is also
883.
879.
879.
199). Figure 200 shows the
Data
ACK ACK
Byte
N Bytes + ACK
Order Number: 306262-004US
2
C Bus
STOP
B4263-01
August 2006