Udc Endpoint 1 Control/Status Register; Transmit Fifo Service (Tfs); Transmit Packet Complete (Tpc); Flush Tx Fifo (Ftf) - Intel IXP45X Developer's Manual

Bits
2
1
0
8.5.3

UDC Endpoint 1 Control/Status Register

The UDC Endpoint 1control status register contains 6 bits that are used to operate
endpoint 1, a Bulk IN endpoint.
8.5.3.1

Transmit FIFO Service (TFS)

The transmit FIFO service bit is active if one or fewer data packets remain in the
transmit FIFO. TFS is cleared when two complete packets of data remain in the FIFO. A
complete packet of data is signified by loading 64 bytes of data or by setting
UDCCS1[TSP].
8.5.3.2

Transmit Packet Complete (TPC)

The transmit packet complete bit is set by the UDC when an entire packet is sent to the
host. When this bit is set, the IR1 bit in the appropriate UDC status/interrupt register is
set if transmit interrupts are enabled. This bit can be used to validate the other status/
error bits in the endpoint 1control/status register.
The UDCCS1[TPC] bit is cleared by writing a 1 to it. This clears the interrupt source for
the IR1 bit in the appropriate UDC status/interrupt register, but the IR1 bit must also
be cleared.
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC
issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been
triggered by writing 64 bytes or setting UDCCS1[TSP].
8.5.3.3

Flush Tx FIFO (FTF)

The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit's read value is 0.
8.5.3.4

Transmit Underrun (TUR)

The transmit underrun bit is set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, NAK handshakes are sent to the host.
UDCCS1[TUR] does not generate an interrupt and is for status only. UDCCS1[TUR] is
cleared by writing a 1 to it.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
296
® ®
Intel IXP45X and Intel
Register
Name
Flush Tx FIFO (always read 0/write 1 to set)
FTF
1 = Flush the contents of Tx FIFO.
IN packet ready (always read 0/write 1 to set).
IPR
1 = IN packet ready.
OUT packet ready (read/write 1 to clear)
OPR
1 = OUT packet ready.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS0
(Sheet 2 of 2)
Description
Controller
(UDCCS1)
August 2006
Order Number: 306262-004US