Pci Controller Control And Status Register - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
10.5.3.8

PCI Controller Control and Status Register

Register Name:
Block
0xC00000
Base Address:
Control and status for the PCI Controller.
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
Register
Bits Name
31:1
reserved reserved – read as 0
7
PCI Reset. When set to a 1, resets the PCI controller and floats the
16 PRST outputs (even in the middle of a PCI transaction). Setting PRST does not
park the bus.
Initialization Complete. When at a logic 0 state, forces the PCI Controller
15 IC Target Interface to retry PCI cycles. When set to a 1, PCI cycles will be
accepted.
14:9 reserved reserved – read as 0
Assert System Error. When set to a 1, the PCI_SERR_N output will be
8 ASE
asserted for 1 PCI clock cycle if the pci_srcr.SER bit is set.
7:6 reserved reserved – read as 0
Doorbell Test mode enable. When set to a 1, the doorbell registers
5 DBT pci_ahbdoorbell, pci_pcidoorbell become normal read/write registers from
the AHB bus.
AHB big-endian addressing. When 0, little-endian addressing is employed
4 ABE on both AHB master and slave interfaces. When 1, big-endian addressing
is implemented.
PCI byte swap. Controls byte lane data routing between PCI and AHB
3 PBS busses during PCI Target accesses of the AHB bus. When 1, byte lane
swapping is performed. When 0, no swapping is done.
AHB byte swap. Controls byte lane data routing between PCI and AHB
2 ABS busses during AHB Slave accesses of the PCI bus. When 1, byte lane
swapping is performed. When 0, no swapping is done.
Arbiter enable status. Indicates the state of the EX_ADDR[2] at the
1 ARBEN deassertion of RESET_IN_N.
Note:
Host status. Indicates the state of the EX_ADDR[1] at the deassertion of
0 HOST RESET_IN_N.
Note:
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Offset Address
Description
Reset value is dependent on expansion bus strapping.
Reset value is dependent on expansion bus strapping.
Intel
pci_csr
0x1c
IC reserved
pci_csr
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0x0000000x
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
(Rsv'd)
Reset PCI AHB
Value Access Access
0x0000 RO
0x0 RO
0 RO
0x00 RO
0 RO
00 RO
0 RO
0 RO
0 RO
0 RO
0 or 1 RO
0 or 1 RO
Develepor's Manual
0
RO
RW
RW
RO
RW
RO
RW
RW
RW
RW
RO
RO
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