Ahb Master Reads; Ahb Slave Interface - Intel IXP45X Developer's Manual

All AHB burst write transfers are disconnected at the 8-word address boundary. If the
Write FIFO becomes empty during the transfer, the AHB Master Interface disconnects
the transfer by driving IDLE cycles on the bus. When data is available again in the FIFO,
the bus is re-acquired and the transfer continues.
Data parity errors received from the Receive FIFO are ignored as far as AHB master
operations are concerned, however the pci_isr.PPE CSR bit is set to capture the error.
10.3.2.9

AHB Master Reads

If the AHB Master Interface receives a Memory Read, Memory Read Line or Memory
Read Multiple command from the PCI target, the BAR ID and byte enables are
examined to determine the appropriate operation:
• If the BAR ID indicates a CSR access (BAR 4), CSR access is requested and, when
granted, a single word read is performed using the supplied address. An AHB
master operation is not performed.
• If the BAR ID indicates a memory access (BARs 0-3), an INCR word read operation
is started on the bus and continues until the PCI Initiator Interface indicates that
the requesting master has terminated the transfer. Any unused data in the Initiator
Read FIFO is discarded.
• If the BAR ID indicates an I/O access (BAR5), a single word read is performed if all
byte enables are asserted, otherwise, a single byte read operation is performed for
each byte that is enabled.
All AHB burst read transfers are disconnected at the 8-word address boundary. If the
Read FIFO becomes full during the transfer, the AHB Master Interface disconnects the
transfer by driving IDLE cycles on the bus. When room is available in the FIFO again,
the bus is re-acquired and the transfer continues.
10.3.2.10

AHB Slave Interface

The AHB Slave Interface provides external AHB masters with read/write access to
external PCI targets, PCI Controller PCI Configuration registers, and local PCI Controller
CSRs. The interface supports both little-endian and big-endian addressing. AHB Slave
accesses are processed by converting the AHB transaction to a PCI transaction with PCI
address, Command, and byte enables provided to the PCI Core. The PCI Core then
executes the requested PCI transaction and provides status and read data to the AHB
Slave.
10.3.2.10.1 AHB-to-PCI Address Translation
For each of the four 16MB memory ranges, the lower 24 bits of the AHB address map to
the lower 24 PCI address bits and an 8-bit field in the PCI_PCIMEMBASE register
provides the upper 8 address bits of the PCI address. Bits 24 and 25 of the AHB
address determine which of the 8-bit fields in PCI_PCIMEMBASE is used. In this
manner, the Intel XScale processor can map each range to any 16MB region in the full
4GB PCI address space by appropriately initializing the four base address fields in
pci_pcimembase. See
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
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Intel IXP45X and Intel
Figure 92 for details.
IXP46X Product Line of Network Processors—PCI Controller
August 2006
Order Number: 306262-004US