Intel IXP45X Developer's Manual page 22

19.5.2.1 Time Sync Control Register....................................................... 839
19.5.2.2 Time Sync Event Register ......................................................... 840
19.5.2.3 Addend Register...................................................................... 840
19.5.2.4 Accumulator Register ............................................................... 841
19.5.2.5 Test Register .......................................................................... 842
19.5.2.6 RawSystemTime_Low Register .................................................. 843
19.5.2.7 RawSystemTime_High Register ................................................. 843
19.5.2.8 SystemTime_Low Register........................................................ 844
19.5.2.9 SystemTime_High Register ....................................................... 844
19.5.2.10TargetTime_Low Register ......................................................... 845
19.5.2.11TargetTime_High Register ........................................................ 845
19.5.2.12Auxiliary Slave Mode Snapshot Low Register - ASMS_Low ............ 846
19.5.2.13Auxiliary Slave Mode Snapshot High Register - ASMS_High .......... 846
19.5.2.14Auxiliary Master Mode Snapshot Low Register - AMMS_Low .......... 847
19.5.2.15Auxiliary Master Mode Snapshot High Register - AMMS_High ........ 847
19.5.2.16TS_Channel_Control Register (Per Channel)................................ 848
19.5.2.17TS_Channel_Event Register (Per Channel) .................................. 849
19.5.2.18XMIT_Snapshot_Low Register (Per Channel) ............................... 850
19.5.2.19XMIT_Snapshot_High Register (Per Channel) .............................. 851
19.5.2.20RECV_Snapshot Low Register (Per Channel) ............................... 852
19.5.2.21RECV_Snapshot High Register (Per Channel)............................... 853
19.5.2.22SourceUUID0_Low Register (Per Channel) .................................. 854
19.5.2.23SequenceID/SourceUUID_High Register (Per Channel) ................. 855
20.0 Synchronous Serial Port .........................................................................................857
20.1 SSP Operation ................................................................................................. 857
20.1.1 Processor-Initiated Data Transfer............................................................ 857
20.2 Data Formats .................................................................................................. 858
20.2.1 Serial Data Formats for Transfer to/from Peripherals ................................. 858
20.2.1.1 SSP Format - Detail ............................................................... 859
20.2.1.2 SPI Format - Detail ................................................................ 859
20.2.1.3 Microwire* Format - Details..................................................... 861
20.2.2 Parallel Data Formats for Buffer Storage .................................................. 862
20.3 Buffer Operation .............................................................................................. 862
20.4 Baud-Rate Generation ...................................................................................... 863
20.5 SSP Serial Port Registers .................................................................................. 863
20.5.1 SSP Control Register 0 (SSCR0).............................................................. 864
20.5.1.1 Data Size Select (DSS) ............................................................ 864
20.5.1.2 Frame Format (FRF) ................................................................ 864
20.5.1.3 External Clock Select (ECS) ...................................................... 864
20.5.1.4 Synchronous Serial Port Enable (SSE) ........................................ 864
20.5.1.5 Serial Clock Rate (SCR)............................................................ 865
20.5.2 SSP Control Register 1 (SSCR1).............................................................. 866
20.5.2.1 Receive FIFO Interrupt Enable (RIE) .......................................... 866
20.5.2.2 Transmit FIFO Interrupt Enable (TIE) ......................................... 866
20.5.2.3 Loop Back Mode (LBM)............................................................. 866
20.5.2.4 Serial Clock Polarity (SPO)........................................................ 867
20.5.2.5 Serial Clock Phase (SPH) .......................................................... 867
20.5.2.6 National Microwire* Data Size (MWDS) ...................................... 868
20.5.2.7 Transmit FIFO Interrupt Threshold (TFT) .................................... 868
20.5.2.8 Receive FIFO Interrupt Threshold (RFT)...................................... 868
20.5.2.9 Enable FIFO Write/Read Function (EFWR) ................................... 868
20.5.2.10Select FIFO for Enable FIFO Write/Read (STRF) ........................... 868
20.5.3 SSP Status Register .............................................................................. 869
20.5.3.1 Transmit FIFO Not Full Flag (TNF) (Read-Only, Non-Interruptible).. 870
20.5.3.2 Receive FIFO Not Empty Flag (RNE) (Read-Only, Non-Interruptible) ....
20.5.3.3 SSP Busy Flag (BSY) (Read-Only, Non-Interruptible).................... 870
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
22
® ®
Intel IXP45X and Intel
870
IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US