Udc Endpoint 0 Control/Status Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Register Name:
0XC800B000
Hex Offset Address:
Register
Universal Serial Bus Device Controller Control Register
Description:
Access: Read/Write and Read-Only
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.2

UDC Endpoint 0 Control/Status Register

The UDC endpoint 0 control/status register contains seven bits that are used to operate
endpoint 0 (control endpoint).
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use
Reset interrupt mask (read/write).
REM 0 = Reset interrupt enabled.
1 = Reset interrupt disabled.
Reset interrupt request (read/write 1 to clear).
RSTIR
1 = UDC was reset by the host.
Suspend/resume interrupt mask (read/write).
SRM 0 = Suspend/resume interrupt enabled.
1 = Suspend/resume interrupt disabled.
Suspend interrupt request (read/write 1 to clear).
SUSIR
1 = UDC received suspend signalling from the host.
Resume interrupt request (read/write 1 to clear).
RESIR
1 = UDC received resume signalling from the host.
Device Resume (read/write 1 to set).
RSM 0 = Maintain UDC suspend state
1= Force UDC out of suspend
UDC active (read-only).
UDA 0 = UDC currently inactive.
1 = UDC currently active.
UDD enable (read/write).
UDE 0 = UDD disable
1 = UDD enabled, UDC+ and UDC- used for USB serial transmission/reception.
Intel
UDCCR
0x000000A0
Reset Hex Value:
UDCCR
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
8 7 6 5 4 3 2 1
1 0 1 0 0 0 0
(UDCCS0)
Developer's Manual
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