Setting The Baud Rate; Setting Data Bits/Stop Bits/Parity; Typical Baud-Rate Settings - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
14.4.1

Setting the Baud Rate

Each UART contains a programmable baud-rate generator that is capable of taking the
14.7456 MHz, input clock (clk_uart) and dividing it by any divisor ranging from 1 to
16
(2 1). The output frequency of the baud-rate generator is 16 times the baud rate.
–
So, if a 1,200 Baud rate was required, the output frequency of the baud-rate generator
would be 1,200 KHz *16 = 19,200 KHz.
Two 8-bit registers store the divisor in a 16-bit binary format: the Divisor Latch Low
Register (DLL) and the Divisor Latch High Register (DLH). The Divisor Latch Low
register makes up the lower eight bits of the 16-bit divisor and the Divisor Latch High
register makes up the upper eight bits of the 16-bit divisor.
The two Divisor Latch registers must be loaded during initialization to ensure proper
operation of the baud-rate generator. If both Divisor Latches are loaded with 0, the 16X
output clock is stopped. A Divisor value of 0 in the Divisor Latch Low Register is not
allowed.
The reset value of the divisor is hexadecimal 0x0002. The value of hexadecimal 0x0002
implies a value of hexadecimal 0x00 in the Divisor Latch High Register and a value of
hexadecimal 0x02 in the Divisor Latch Low Register. The Divisor Latch High Register
and Divisor Latch Low Register can only be written after the DLAB bit (bit 7 of the Serial
Line Control Register) is set to logic 1.
The baud rate of the UART transmit and receive data is given by:
Baud Rate = 14.7456 MHz/
(16xDivisor)
Table 244
Table 244.

Typical Baud-Rate Settings

Divisor
Latch High
Register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x03
14.4.2

Setting Data Bits/Stop Bits/Parity

The Line Control Register (LCR) is an 8-bit register that enables the system
programmer to specify the format of the asynchronous data communications exchange.
The serial data format consists of a start bit (logic 0), five to eight data bits, an optional
August 2006
Order Number: 306262-004US
shows some commonly used baud rates.
Divisor Latch
Low Register
Hexadecimal
0x01 0x0001
0x02 0x0002
0x04 0x0004
0x08 0x0008
0x10 0x0010
0x20 0x0020
0x30 0x0030
0x40 0x0040
0x80 0x0080
0xC0 0x00C0
0x80 0x0180
0x00 0x0300
® ®
IXP45X and Intel
Divisor
Decimal
1
2
4
8
16
32
48
64
96
192
384
768
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
IXP46X
Baud Rate
Generator Clock Baud Rate
Output
14.7456 MHz 921,600
7.3728 MHz 460,800
3.6864 MHz 230,400
1.8432 MHz 115,200
921.6 KHz 57,600
460.8 KHz 28,800
307.2 KHz 19,200
230.4 KHz 14,400
115.2 KHz 9,600
76.8 KHz 4,800
38.4 KHz 2,400
19.2 KHz 1,200
Developer's Manual
753