High-Speed Serial Interface Receive Operation - Intel IXP45X Developer's Manual

length of the lookup table can be programmed as needed. Selecting a timeslot as HDLC
tells the HSS core that the timeslot should be stored in a HDLC FIFO (the particular
HDLC FIFO depends on what location in the lookup table was programmed, see
Figure 165 on page 728
In the case where dual MVIP or normal E1/T1 protocols are operating, not all of the
lookup table space will be used. The frame size programmed indicates the number of
locations used in lookup table.
In the case of GCI, the lookup tables should be programmed to VOICE.
To support software ATM-TC (Transmission Convergence) operations, a HEC generator
and an ATM scrambler are located within the HSS, note that only two are employed in
total, 1TX and 1RX (not one per core).
13.1.1

High-Speed Serial Interface Receive Operation

Each High-Speed Serial Interface contains five receive FIFOs and four receive FIFOs
intended for facilitating the use of HDLC. Each is two 32-bit words in length. The four
receive FIFOs are further divided into two buffers, each one 32-bit word in length.
These FIFOs are hardware support added to facilitate the implementation of four HDLC
channels and do not preclude the implementation of more HDLC channels using the
Network Processor Engine core and the HDLC coprocessor connected.
The HSS interface will be filling one buffer while the NPE Core empties the other buffer.
The fifth receive FIFO is intended for voice-processing support and is four 32-bit words
in length. This receive FIFO is split into two buffers, each buffer two 32-bit words in
length.
These buffers also behave in a ping-pong fashion, so the NPE Core will read two 32-bit
words at a time for processing. The location that each received byte is placed into these
FIFOs is a function of a user programmable look-up table (LUT) and the protocol that is
being implemented.
The look-up table will characterize each received byte as one of four types:
• Unassigned
• Voice
This characterization will be assigned on a time-slot basis using Intel-supplied APIs. For
example, time slot 0 may be defined as a voice cell, time slot 1 as an HDLC wrapped
packet, time slot 2 as an undefined time slot, and time slot 3 defined as an 56-K mode
cell.
When the HSS receive interface processes the first byte (time slot 0), the look-up table
will indicate that this received byte is a voice cell and needs to be placed into the Voice
FIFO. Likewise, when the high-speed serial receive interface processes the second byte
(time slot 1), the look-up table will indicate that this received byte is an HDLC cell and
needs to be placed into one of the HDLC FIFOs. The actual FIFO the byte is placed in is
dependent on the protocol implemented and the FIFO arrangement.
For more details, see the Intel
When the high-speed serial receive interface processes the third byte (time slot 2), the
look-up table will indicate that this received byte is an unassigned cell and needs to be
discarded. When the high-speed serial receive interface processes the fourth byte (time
slot 3), the look-up table will indicate that this received byte is a 56-K mode cell and
will also be placed into the Voice FIFO.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
724
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Intel IXP45X and Intel
for more details).
• HDLC
• 56-K mode
®
IXP400 Software Programmer's Guide.
IXP46X Product Line of Network Processors—HSS Coprocessor
August 2006
Reference Number: 004US