Loading Ic During Reset; Format Of Ldic Cache Functions - Intel IXP45X Developer's Manual

Intel
Figure 23.

Format of LDIC Cache Functions

All packets are 33 bits in length. Bits [2:0] of the first packet specify the function to
execute. For functions that require an address, bits[32:6] of the first packet specify an
eight-word aligned address (Packet1[32:6] = VA[31:5]). For Load Main IC and Load
Mini IC, eight additional data packets are used to specify eight Intel
instructions to be loaded into the target instruction cache. Bits[31:0] of the data
packets contain the data to download. Bit[32] of each data packet is the value of the
parity for the data in that packet.
As shown in
33-bit packet, the host must take the JTAG state machine into the Update_DR state.
After the host does an Update_DR and returns the JTAG state machine back to the
Shift_DR state, the host can immediately begin shifting in the next 33-bit packet.
3.6.14.4

Loading IC During Reset

Code can be downloaded into the instruction cache through JTAG during a processor
reset. This feature is used during software debug to download the debug handler prior
to starting an application program. The downloaded handler can then intercept the
reset vector and do any necessary setup before the application code executes
In general, any code downloaded into the instruction cache through JTAG, must be
downloaded to addresses that are not already valid in the instruction cache. Failure to
meet this requirement will result in unpredictable behavior by the processor. During a
processor reset, the instruction cache is typically invalidated, with the exception of the
following modes:
• LDIC mode — Active when LDIC JTAG instruction is loaded in the JTAG IR; prevents
the mini instruction cache and the main instruction cache from being invalidated
during reset.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
142
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Invalidate IC Line
Invalidate Mini IC
Load Main IC
(CMD = 0b010)
and
Load Mini IC
(CMD = 0b011)
Figure 23, the first bit shifted in TDI is bit 0 of the first packet. After each
VA[31:5] 0 0 0 0 0
32 31 5 2
x x . . . x 0 0 0 0 0
32 31 5 2
P
Data Word 7
.
.
.
Data Word 0
P
VA[31:5] 0 0 0
CMD
32 31 5 2
®
Processor
0
0
1
- indicates first
bit shifted in
0
- indicates last
bit shifted in
0
B4350-01
®
StrongARM
August 2006
Order Number: 306262-004US
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