Intel IXP45X Developer's Manual page 81

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Intel XScale Processor—Intel
Example 5. Enabling the Instruction Cache
; Enable the ICache
MRC P15, 0, R0, C1, C0, 0
ORR R0, R0, #0x1000
MCR P15, 0, R0, C1, C0, 0
CPWAIT
The entire instruction cache along with the fetch buffers are invalidated by writing to
coprocessor 15, register 7. (See
command.) The invalidate command does not unlock any lines that were locked in the
instruction cache nor does it invalidate those locked lines. To invalidate the entire cache
including locked lines, the unlock instruction cache command needs to be executed
before the invalidate command. The unlock command can also be found in
"Cache Lock-Down Functions" on page
There is an inherent delay from the execution of the instruction cache invalidate
command to where the next instruction will see the result of the invalidate. The
following routine can be used to guarantee proper synchronization.
Example 6. Invalidating the Instruction Cache
MCR P15,0,R1,C7,C5,0
CPWAIT
; The instruction cache is guaranteed to be invalidated at this point; the next
; instruction sees the result of the invalidate command.
The Intel XScale processor also supports invalidating an individual line from the
instruction cache. See
command.
Software has the ability to lock performance critical routines into the instruction cache.
Up to 28 lines in each set can be locked; hardware will ignore the lock command if
software is trying to lock all the lines in a particular set (i.e., ways 28-31can never be
locked). When all ways in a particular set are requested to be locked, the instruction
cache line will still be allocated into the cache but the lock will be ignored. The round-
robin pointer will stay at way 31 for that set.
Cache lines can be locked into the instruction cache by initiating a write to
coprocessor 15. (See
exact command.) Register Rd contains the virtual address of the line to be locked into
the cache.
There are several requirements for locking down code:
• The routine used to lock lines down in the cache must be placed in non-cacheable
memory, which means the MMU is enabled.
As a result: no fetches of cacheable code should occur while locking instructions
into the cache.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Table 20, "Cache Functions" on page 104
; Invalidate the instruction cache and branch
; target buffer
Table 20, "Cache Functions" on page 104
Table 22, "Cache Lock-Down Functions" on page 105
Intel
; Get the control register
; set bit 12 -- the I bit
; Set the control register
105.
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
for the exact
Table 22,
for the exact
for the
Developer's Manual
81