Intel
3.5.1.3
Register 2: Translation Table Base Register
Table 16.
Translation Table Base Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:14
13:0
3.5.1.4
Register 3: Domain Access Control Register
Table 17.
Domain Access Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D15
D14
reset value: unpredictable
Bits
31:0
3.5.1.5
Register 4: Reserved
Register 4 is reserved. Reading and writing this register yields unpredictable results.
3.5.1.6
Register 5: Fault Status Register
The Fault Status Register (FSR) indicates which fault has occurred, which could be
either a prefetch abort or a data abort. Bit 10 extends the encoding of the status field
for prefetch aborts and data aborts. The definition of the extended status field is found
in
"Event Architecture" on page
the exact source of the event is found in the debug control and status register (CP14,
register 10). When bit 9 is set, the domain and extended status field are undefined.
Upon entry into the prefetch abort or data abort handler, hardware will update this
register with the source of the exception. Software is not required to clear these fields.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
102
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—Intel XScale
Translation Table Base
Access
Read / Write
Read-unpredictable / Write-as-Zero
D13
D12
D11
D10
Access
Read / Write
Translation Table Base - Physical address of the base
of the first-level table
Reserved
D9
D8
D7
D6
Access permissions for all 16 domains - The meaning
of each field can be found in the ARM* Architecture
Reference Manual.
177. Bit 9 indicates that a debug event occurred and
®
8
7
6
5
4
3
Description
8
7
6
5
4
3
D5
D4
D3
D2
D1
Description
August 2006
Order Number: 306262-004US
Processor
2
1
0
2
1
0
D0
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