C Bus Interface Unit Block Diagram; C Bus Definitions - Intel IXP45X Developer's Manual

Intel
2
The I C unit's state machines and functionality are partially controlled by using local
memory mapped registers (MMRs) that store configuration and operation information.
The registers are controlled from the APB bus and reside in the i2c_registers block.
2
Figure 190. I

C Bus Interface Unit Block Diagram

SCL
2
I C Bus
Monitor
I2C_int_1
21.4 Theory of Operation
2
The I C bus defines a serial protocol for passing information between agents on the I
bus using a two pin interface. The interface consists of an SDA line and an SCL. Each
device on the I
transmitter or as a receiver. In addition to transmitter and receiver, the I
the concept of master and slave.
Table 276
2
Table 276. I C Bus Definitions (Sheet 1 of 2)
2
I C Device
Transmitter
Receiver
Master
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
876
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
SDA
2
I C Data Buffer Register (IDBR)
2
I C Slave Address Register (ISAR)
SCL
2
I C Clock Count Register (ICCR)
Count
Generator
2
C bus is recognized by a unique 7-bit address and can operate as a
2
lists the I C device types.
2
Sends data to the I
Receives data from the I
Initiates a transfer, generates the clock signal, and terminates the transactions.
Serial Shift Register
2
I C Control Register (ICR)
2
I C Status Register (ISR)
Internal Bus Interface
Internal Bus Address and Control Signals
APB Bus
Definition
C bus.
2
C bus.
Address
Decode
B4271-01
2
C
2
C bus uses
August 2006
Order Number: 306262-004US