Page Hit/Miss Determination - Intel IXP45X Developer's Manual

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Memory Controller—Intel
For example, assume an internal bus master issues a write to DDRI SDRAM memory
space via the Internal Bus Memory Port. The address specified on ADDR[31:0] is
0000 0010H.
If 32-bit data bus width is enabled, the MCU shifts ADDR[31:2] by one bit to the left
before translating the address to DDRI_MA[13:0]. Therefore, the column address
becomes four for the first write transaction.
The MCU for the IXP45X/IXP46X network processors only supports a 32-bit data bus,
although future products may support a 64-bit data bus width. The data bus width is
selected by bit 2 of the SDCR (see
page 633). The power-on default is a 64-bit bus width, but for the IXP45X/IXP46X
network processors, the bus width MUST always be programmed to be 32-bit bus
width.
11.2.2.6

Page Hit/Miss Determination

The page size is based on the DDRI technology as specified in
keeps up to eight pages open simultaneously, one page each of:
• Bank0/Leaf0
• Bank0/Leaf1
• Bank0/Leaf2
• Bank0/Leaf3
• Bank1/Leaf0
• Bank1/Leaf1
• Bank1/Leaf2
• Bank1/Leaf3
Figure 104
The MCU logic determines the hit/miss status for reads and writes. For a new DDRI
SDRAM transaction, the MCU compares the address of the current transaction with the
address stored in the appropriate page address register. Given the supported DDRI
SDRAM devices and two banks, there are eight pages kept open simultaneously. The
DDRI SDRAM chip enables DDRI_CS_N[1:0] and leaf selects DDRI_BA[1:0] determine
which page address to compare.
If the current transaction misses the open page selected then the MCU closes the open
page pointed to by DDRI_CS_N and DDRI_BA by issuing a precharge command. The
MCU opens the current page with a row-activate command and the transaction
completes with a read or write command. When the MCU opens the current page, the
row address from the corresponding memory transaction queue is stored in the page
address register pointed to by DDRI_CS_N and DDRI_BA so it may be compared for
future transactions. See
row address.
Once the MARB issues a command to the MCU DDRI Control Block, the paging logic
makes a hit/miss comparison. The performance is best for page hits and therefore the
MCUs behavior is different for the hit and miss scenario.
For a page hit, the MCU does not need to open the page and avoids the RAS-to-CAS
delay achieving greater performance. The waveform for a write including the row
activation in the case of a page miss is illustrated in
cycles required for row activation are saved resulting in lower first word write latency.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
illustrates the logical flow of page hit determination
Table 208,
"DDRI SDRAM Control Register 0 SDCR0" on
Table 209, and Table 210
Figure
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Table 203. The MCU
for address mapping to
115. For a page hit, the two
Developer's Manual
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