Intel IXP45X Developer's Manual page 608

A read that misses the open pages encounters a miss penalty because the currently
open page needs to be closed before the read can be issued to the new page. Refer to
Section 11.2.2.6, "Page Hit/Miss Determination"
page hit occurs, steps 3-4 are skipped by the MCU.
3. The DDRI SDRAM Control Block closes the currently open page by issuing a
precharge command to the currently open row. (Not depicted in
— The DDRI SDRAM Control Block waits T
issuing the row-activate command for the new read transaction.
4. The row-activate command enables the appropriate row.
— The DDRI SDRAM Control Block asserts DDRI_RAS_N, de-asserts DDRI_WE_N,
and drives the row address on DDRI_MA[13:0].
5. In the following cycle in the case of a page hit or after T
page miss, the DDRI SDRAM Control Block asserts DDRI_CAS_N, de-asserts
DDRI_WE_N, and places the column address on DDRI_MA[13:0]. This initiates the
burst read cycle.
6. After the CAS latency expires, the DDRI SDRAM device drives data to the MCU. A
CAS latency of 2 is depicted in
7. Upon receipt of the data, the DDRI SDRAM Control Block calculates the ECC code
from the data and compares it with the ECC returned by the DDRI SDRAM array.
Section 11.2.3, "Error Correction and Detection"
more detail.
8. Assuming the calculated ECC matches the read ECC, the DDRI SDRAM Control
Block drives the data back to the corresponding memory transaction queue.
• For each burst read issued, the memory controller increments the column address
by four.
The MCU continues to return data to the corresponding memory transaction queue
based on the byte count of the transaction.
Note: The burst cycle continues within the DDRI SDRAM devices unless the next read/write
transaction is ready to be issued. The current DDRI SDRAM burst read may be
interrupted by issuing the next read or write command.
The MCU divides transactions if they cross a page boundary. For read transactions, the
transactions will be completed in multiple completions which end at page boundaries.
Write transactions will receive posted data to the inbound memory transaction queue
up to a full posted write queue (32 Bytes). Multiple write commands will then be issued
to the DDRI SDRAM to complete the write of data to the multiple pages.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
608
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller
for the paging algorithm details. If a
cycles after the precharge before
rp
Figure 114.
explains the ECC algorithm in
Figure 114.)
cycles in the case of a
rcd
August 2006
Order Number: 306262-004US