The Pid Register Affect On Addresses; Register 14: Breakpoint Registers; Register 15: Coprocessor Access Register; Accessing The Debug Registers - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
3.5.1.14

The PID Register Affect On Addresses

All addresses generated and used by User Mode code are eligible for being "PIDified" as
described in the previous section. Privileged code, however, must be aware of certain
special cases in which address generation does not follow the usual flow.
The PID register is not used to remap the virtual address when accessing the Branch
Target Buffer (BTB). Any writes to the PID register invalidate the BTB, which prevents
any virtual addresses from being double mapped between two processes.
A breakpoint address (see
expressed as an MVA when written to the breakpoint register. This requirement means
the value of the PID must be combined appropriately with the address before it is
written to the breakpoint register. All virtual addresses in translation descriptors (see
"Memory Management Unit" on page
3.5.1.15

Register 14: Breakpoint Registers

The Intel XScale processor contains two instruction breakpoint address registers
(IBCR0 and IBCR1), one data breakpoint address register (DBR0), one configurable
data mask/address register (DBR1), and one data breakpoint control register (DBCON).
The Intel XScale processor also supports a 256-entry, trace buffer that records program
execution information. The registers to control the trace buffer are located in CP14.
Refer to
Intel XScale processor.
Table 27.

Accessing the Debug Registers

Access Instruction Breakpoint
Control Register 0 (IBCR0)
Access Instruction Breakpoint
Control Register 1(IBCR1)
Access Data Breakpoint Address
Register (DBR0)
Access Data Mask/Address
Register (DBR1)
Access Data Breakpoint Control
Register (DBCON)
3.5.1.16

Register 15: Coprocessor Access Register

This register is selected when opcode_2 = 0 and CRm = 1.
This register controls access rights to all the coprocessors in the system except for
CP15 and CP14. Both CP15 and CP14 can only be accessed in privilege mode. This
register is accessed with an MCR or MRC with the CRm field set to 1.
This register controls access to CP0, atypical use for this register is for an operating
system to control resource sharing among applications. Initially, all applications are
denied access to shared resources by clearing the appropriate coprocessor bit in the
Coprocessor Access Register. An application may request the use of a shared resource
(e.g., the accumulator in CP0) by issuing an access to the resource, which will result in
an undefined exception. The operating system may grant access to this coprocessor by
setting the appropriate bit in the Coprocessor Access Register and return to the
application where the access is retried.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
"Register 14: Breakpoint Registers" on page
"Software Debug" on page 111
Function
69) are MVAs.
for more information on these features of the
opcode_2 CRm
0b000 0b1000
0b000 0b1001
0b000 0b0000
0b000 0b0011
0b000 0b0100
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
107) must be
Instruction
MRC p15, 0, Rd, c14, c8, 0 ; read
MCR p15, 0, Rd, c14, c8, 0 ; write
MRC p15, 0, Rd, c14, c9, 0 ; read
MCR p15, 0, Rd, c14, c9, 0 ; write
MRC p15, 0, Rd, c14, c0, 0 ; read
MCR p15, 0, Rd, c14, c0, 0 ; write
MRC p15, 0, Rd, c14, c3, 0 ; read
MCR p15, 0, Rd, c14, c3, 0 ; write
MRC p15, 0, Rd, c14, c4, 0 ; read
MCR p15, 0, Rd, c14, c4, 0 ; write
Developer's Manual
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