Initiated Pci I/O Write Cycle; Initiated Burst Memory Read Transaction - Intel IXP45X Developer's Manual

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PCI Controller—Intel IXP45X and Intel
Figure 87.

Initiated PCI I/O Write Cycle

PCI_CLK
INT_REQ_N
INT_GNT_N
PCI_FRAME_N
PCI_AD (31:0)
PCI_IDSEL
PCI_CBE_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
10.2.7.9

Initiated Burst Memory Read Transaction

The following transaction is a two word bursting PCI Memory Read Cycle initiated from
the IXP45X/IXP46X network processors. This diagram is to understand the inner
workings of PCI transfers and may not reflect actual operation of the PCI Controller
implemented on the IXP45X/IXP46X network processors. The transaction is initiated to
initial address location hexadecimal 0x00000014. The value of binary 00 in PCI_AD
(1:0) indicates that this is a linear increment transfer type. The second data word
transferred will be from address hexadecimal 0x00000018.
A hexadecimal value of 0x6 written on the PCI_CBE_N bus during the address phase
signifies that this is a PCI Bus Memory Read Cycle. All byte-enables are active for the
transaction.
A maximum burst length of eight 32-bit words is supported for initiated Memory Cycle
transactions from the IXP45X/IXP46X network processors.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
0x00000015 DATA
0x3 0xD
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Intel IXP45X and Intel
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IXP46X Product Line of Network Processors
Develepor's Manual
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