Pci-To-Ahb Dma Pci Address Register 0; Pci-To-Ahb Dma Length Register 0 - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
10.5.3.24

PCI-to-AHB DMA PCI Address Register 0

Register Name:
Block
0xC00000
Base Address:
Source address on the PCI bus for PCI-to-AHB DMA transfers.
Paired with pci_ptadma1_pciaddr to allow buffering of DMA
Register Description:
transfer requests.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:2 address PCI word address
1:0 Lower PCI address bits hard-wired to zero.
10.5.3.25

PCI-to-AHB DMA Length Register 0

Register Name:
Block
0xC00000
Base Address:
Provides word count and control for PCI-to-AHB DMA transfers.
Paired with pci_ptadma1_length to allow buffering of DMA transfer
Register Description:
requests.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
EN (Rsvd) DS
Register
Bits Name
Channel enable. When set to a 1, executes a DMA transfer if wordcount is
31 EN nonzero. When 0, the channel is disabled. Hardware clears this bit when
the DMA transfer is complete.
30:2
reserved Reserved. Read as 0.
9
Data Swap indicator. When set to a 1, data from the PCI bus is byte
28 DS
swapped before being sent to the AHB bus. When 0, no swapping is done.
27:1
reserved Reserved. Read as 0.
6
15:0 wordcount Number of words to transfer.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Offset Address
address
Description
Offset Address
(Reserved)
Description
Intel
pci_ptadma0_pciaddr
0x5c
pci_ptadma0_pciaddr
pci_ptadma0_length
0x60
wordcount
pci_ptadma0_length
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
0
Reset PCI AHB
Value Access Access
0x0000
RO
0000
00 RO
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset PCI AHB
Value Access Access
0 RO
00 RO
0 RO
0x000 RO
0x0000 RO
Develepor's Manual
0
0
RW
RO
0
RW
RO
RW
RO
RW
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