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The direction that the FIFO flows is controlled by the UDC. Normally, the UDC is in an
idle state, waiting for the host to send commands. When the host sends a command,
the UDC fills the FIFO with the command from the host and the Intel XScale processor
reads the command from the FIFO when it arrives. The only time the Intel XScale
processor may write the endpoint 0 FIFO is after a valid command from the host is
received and it requires a transmission in response.
Register Name:
0 x C800B080
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 0 Data Register
Description:
Access: Read/Write
31
Bits
31:8
7:0
8.5.31
UDC Data Register 1
Endpoint 1 is a double-buffered bulk IN endpoint that is 64 bytes deep. Data can be
loaded via direct Intel XScale processor writes. Because it is double-buffered, up to two
packets of data may be loaded for transmission.
Register Name:
0 x C800B100
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 1 Data Register
Description:
Access: Write
31
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
342
®
®
Intel
IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Top/bottom of endpoint 0 FIFO data.
DATA
Read Bottom of endpoint 0 FIFO data.
Write Top of endpoint 0 FIFO data.
(Reserved)
X
Resets (Above)
IXP46X Product Line of Network Processors—USB 1.1 Device
UDDR0
0x00000000
Reset Hex Value:
Bits
UDDR0
Description
UDDR1
0x00000000
Reset Hex Value:
Bits
Controller
8
(Data)
Read Access
Write Access
Bottom of
Top of Endpoint
Endpoint 0 FIFO
0 FIFO
(UDDR1)
8
7
6
5
4
3
2
(8-Bit Data)
0
0
0
0
0
0
August 2006
Order Number: 306262-004US
0
1
0
0
0
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