Bit To 32-Bit Addressing; Ddri Sdram Address Translation For 1 Gbitx16 Devices; Bit Data Bus Width - Intel IXP45X Developer's Manual

Table 210.

DDRI SDRAM Address Translation for 1 Gbitx16 Devices

DDRI_MA
13 12
[13:0]
Row
Column
- -
Notes:
1. A10 is used for precharge variations on the read or write command. See
2. For the Leaf Selects, see
3. 1 Gbitx16 addressing requires that ADDR[26] be presented as bit 13 of the row address instead of ADDR[27] as in
Table 208.
Since the MCU supports DDRI SDRAM bursting, the MCU increments the column
address based on the burst length of four for each DDRI SDRAM read or write burst.
The MCU supports a sequential and random burst types. Sequential bursting means
that the address issued to the DDRI SDRAM is incremented by the DDRI SDRAM device
in a linear fashion during the burst cycle. Random bursting means that the address
issued to the DDRI SDRAM is any address in a currently active page.
11.2.2.5

32-Bit Data Bus Width

The MCU supports a 32-bit data bus width and a minimum memory size of 32 Mbytes,
the maximum bus throughput is 1066 Mbytes/sec.
DDRI SDRAM address translation differs between 64- and 32-bit data bus widths. To
generate a 32-bit address to the memory subsystem, the internal address ADDR[31:2]
is shifted to the left by one bit prior to the address translations illustrated in
through Table
See Figure 103
SDRAM address on DDRI_MA[13:0] results in 32-bit addressing.
Figure 103. 64-Bit to 32-Bit Addressing
Example assumes that the 32-
Address for
64-bit Data
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
594
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Intel IXP45X and Intel
11 10 9
1
V
Table 203.
210. This provides the granularity required for a 32-bit wide memory.
for an example of how shifting the address before generating the DDRI
bit address in question has the
same row address independent
of memory bus width.
20H
Data 9
18H
Data 7
10H
Data 5
08H
Data 3
00H
Data 1
IXP46X Product Line of Network Processors—Memory Controller
8 7 6 5
Table 211
SDRAM Column
Address on MA[12:0]
9
8
7
6
5
Data 8
4
Data 6
3
Data 4
2
Data 2
1
Data 0
0
4 3 2 1
for more details.
Table 208
Addr ess for
32-bit Data
Data 9
24H
Data 8
20H
Data 7
1CH
Data 6
18H
Data 5
14H
Data 4
10H
Data 3
0CH
Data 2
08H
Data 1
04H
Data 0
00H
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August 2006
Order Number: 306262-004US
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