Udc Interrupt Control Register 0; Interrupt Mask Endpoint X (Imx), Where X Is 0 Through 7 - Intel IXP45X Developer's Manual

8.5.18

UDC Interrupt Control Register 0

The UICR0 contains eight control bits to enable/disable interrupt service requests from
data endpoints 0 - 7. All of the UICR0 bits are reset to a 1 so interrupts are not
generated on initial system reset.
8.5.18.1

Interrupt Mask Endpoint x (IMx), where x is 0 through 7

The UICR0[IMx] bit is used to mask or enable the corresponding endpoint interrupt
request, USIR0[IRx]. When the mask bit is set, the interrupt is masked and the
corresponding bit in the USIR0 register is not allowed to be set.
When the mask bit is cleared and an interruptible condition occurs in the endpoint, the
appropriate interrupt bit is set. Programming the mask bit to a 1 does not affect the
current state of the interrupt bit. It only blocks future 0-to-1 transitions of the interrupt
bit.
Register Name:
0 x C800B050
Hex Offset Address:
Register
Universal Serial Bus Device Controller Interrupt Control Register 0
Description:
Access: Read/Write and Read-Only
31
Bits
31:8
7
6
5
4
3
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
328
® ®
Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Interrupt Mask for Endpoint 7.
IM7 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt Mask for Endpoint 6.
IM6 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
Interrupt mask for Endpoint 5.
IM5 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
Interrupt mask for Endpoint 4.
IM4 0 = Receive Interrupt enabled.
1 = Receive Interrupt disabled.
Interrupt mask for Endpoint 3.
IM3 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
IXP46X Product Line of Network Processors—USB 1.1 Device
UICR0
0x000000FF
Reset Hex Value:
Bits
UICR0
(Sheet 1 of 2)
Description
Controller
(UICR0)
8 7 6 5 4 3 2 1
1 1 1 1 1 1 1
August 2006
Order Number: 306262-004US
0
1