Configuration Register 0 - Intel IXP45X Developer's Manual

Table 228. Bit Level Definition for each of the Timing and Control Registers (Sheet 2 of 2)
Bits
15:14
13:9
8
7
6
5
4
3
2
1
0
The EXP_TIMING_CS registers may only be written if there is not an outstanding
Expansion bus transaction. Software must ensure that all outstanding Expansion bus
transfers are complete before changing the EXP_TIMING_CS registers.
12.5.9

Configuration Register 0

At power up or whenever RESET_IN_N is asserted, the expansion bus address outputs
are switched to inputs and the states of the bits are captured and stored in
Configuration Register 0, bits 23 through 0. This occurs when PLL_LOCK is deasserted.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
706
® ®
Intel IXP45X and Intel
Name
00 = Configures the Expansion bus for Intel cycles.
01 = Configures the Expansion bus for Motorola cycles.
CYC_TYPE 10 = Configures the Expansion bus for HPI cycles.
11 = Configures the Expansion bus for Micron ZBT cycles
Device Configuration Size. Calculated using the formula:
For Example:
00000 = Address space of 2
00010 = Address space of 2
CNFG[4:0]
10000 = Address space of 2
11100 = Address space of 2
11110 = Address space of 2
00001 = Address space of 2
Synchronous Intel StrataFlash
CYC_TYPE is not programmed to Intel cycles.
Sync_Intel
0 = Target device is not a Synchronous Intel StrataFlash
1 = Target device is a Synchronous Intel StrataFlash
0 = Target device is not one of the IXP45X/IXP46X network
processors
EXP_CHIP
1 = Target device is one of the IXP45X/IXP46X network
processors. This bit must only be set to 1 when CYC_TYPE is
configured to be Intel Cycles and Sync_Intel is set to 0.
Byte read access to Half Word device
BYTE_RD16 0 = Byte access disabled.
1 = Byte access enabled.
HPI HRDY polarity (reserved for EX_CS_N[7:4] only)
HRDY_POL 0 = Polarity low true.
1 = Polarity high true.
0 = Separate address and data buses.
MUX_EN
1 = Multiplexed address / data on data bus.
0 = AHB split transfers disabled.
SPLT_EN
1 = AHB split transfers enabled.
1 = Expansion bus uses 32-bit data bus
WORD_EN
0 = Expansion bus uses 8/16 bit data bus based on BYTE_EN bit
0 = Writes to CS region are disabled.
WR_EN
1 = Writes to CS region are enabled.
0 = Expansion bus uses 16-bit-wide data bus if WORD_EN = 0.
BYTE_EN
1 = Expansion bus uses only 8-bit data bus if WORD_EN = 0.
IXP46X Product Line of Network Processors—Expansion Bus
Description
(HPI reserved for chip selects [7:4] only)
(9+CNFG[4:1]+16*CNFG[0])
SIZE OF ADDR SPACE = 2
9
= 512 Bytes
10
...
17
...
23
24
25
Controller
= 1024 Bytes
= 128 Kbytes
= 8 Mbytes
= 16 Mbytes
= 32Mbytes
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select. This bit must be 0 if
August 2006
Order Number: 306262-004US