Ahb Master Interface - Intel IXP45X Developer's Manual

10.3.2.6.3 Effect on Internal PCI Arbiter
If the internal PCI arbiter is enabled, a low level on exp_rcomp_complete will block all
requests from external PCI masters and cause the arbiter to park the bus on the local
PCI Initiator Interface. This has the effect of preventing any switching on the arbiter
grant outputs. When exp_rcomp_complete is a logic 1, the requests from external
masters are enabled and the arbiter functions normally.
10.3.2.7

AHB Master Interface

The AHB Master Interface provides read/write access to AHB slaves and local CSRs for
transactions generated by external PCI Initiators. It also services read/write requests
from the DMA Controller channels to effect DMA transfers between the AHB and PCI
busses. Both big-endian and little-endian addressing are implemented depending on
the state of the pci_csr.ABE bit. Three virtual AHB masters can initiate transfers using
the AHB Master Interface:
1. Transfers originating from an external PCI master are presented to the AHB Master
Interface by the PCI Target Interface via the Target FIFOs in the PCI Core. The AHB
Master Interface reads the PCI address and control information from the Target
Receive FIFO and translates the PCI transaction to an appropriate AHB transaction.
For writes, data is written to the Target Receive FIFO by the PCI Core and read out
to the AHB bus by the AHB Master Interface. During reads, the AHB Master
Interface performs an appropriate read transaction and writes the data to the
Target Transmit FIFO.
2. The AHB-to-PCI DMA channel uses the AHB Master Interface to read data from an
AHB agent and send a PCI write request to the PCI Core via the Initiator Request
and Initiator Transmit FIFOs.
3. The PCI-to-AHB DMA channel uses the AHB Master Interface to read previously
requested PCI read data from the Initiator Receive FIFO and write this data to an
AHB agent.
Arbitration for control of AHB mastering resources is carried out on two levels. On the
first level, PCI requests and DMA requests alternate for priority access. On the second
level, the two DMA channels alternate for priority access. This arbitration scheme
balances the high bandwidth DMA traffic with the lower bandwidth PCI traffic.
10.3.2.7.1 PCI Address Translation to AHB Address
The PCI address received from the PCI Core is translated to an AHB address as follows:
• The AHB Master Interface reads a BAR indicator (BAR ID) from the Core to
determine which of the 6 PCI Configuration BARs was targeted.
• If one of the lower four BARs was targeted (PCI_BAR0/1/2/3), the bits 23:2 of the
PCI address map to bits 23:2 of the AHB address bits and an 8-bit field in the
PCI_AHBMEMBASE register provides the upper 8 address bits of the AHB address.
In this manner, each 16MB address range on the PCI bus can be mapped to any
16MB region in the full 4GB AHB address space by appropriately initializing the four
base address fields in pci_ahbmembase. Bits 1:0 of the AHB address are derived
from the PCI byte enables.
• If PCI_BAR4 was targeted, the access is directed to the PCI accessible CSRs in the
PCI Controller and no AHB transaction is performed.
• If PCI_BAR5 was targeted, bits 7:2 of the PCI address map to bits 7:2 of the AHB
address bits and the 24-bit IOBase field of the PCI_AHBIOBASE register provides
the upper 24 bits of the AHB address. Bits 1:0 of the AHB address are derived from
the PCI byte enables.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
530
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Intel IXP45X and Intel
Figure 91
IXP46X Product Line of Network Processors—PCI Controller
shows the address translation mechanism.
August 2006
Order Number: 306262-004US