Intel IXP45X Developer's Manual page 711

Expansion Bus Controller—Intel
Processors
Table 231. Expansion Bus Configuration Register 1-Bit Definition (Sheet 2 of 3)
Bit
18
17
16
15
14
13
12
11
Note: For transactions initiated by the Intel XScale
coherency is controlled by a software-programmable, P-attribute bit in the Intel
Line Memory Management Unit (MMU) and the BYTE_SWAP_EN bit. The BYTE_SWAP_EN bit will be
from Expansion bus controller Configuration Register 1, Bit 8. This bit will reset to 0.
The default endian conversion method for IXP45X/IXP46X network processors is address coherency.
This was selected to enable backward compatible with the Intel
The BYTE_SWAP_EN bit is an enable bit that enables data coherency to be performed, based on the
P-attribute bit.
When the bit is 0, address coherency is always performed.
When the bit is 1, the type of coherency depends on the P-attribute bit.
The P-attribute bit is associated with each 1-Mbyte page. The P-attribute bit is output, from the Intel
XScale processor, with any store or load access associated with that page.
Note: When enabling SMII mode for the NPE's during boot-up, the NPE's will need to be reset in software
to ensure a clean transition into SMII mode. Software must execute the following code when
entering SMII mode:
1. Write the Expansion EXP_UNIT_FUSE_RESET register to turn ON the reset for the NPE's.
2. If the PCI interface is not used, the PCI RCOMP bit of the EXP_UNIT_FUSE_RESET register must be
set to a '1'. If the PCI interface is used, the PCI RCOMP bit must be left unchanged at logic '0'.
3. Read the SMII_RCOMP_CSR register, set bit 16 to '1', and write value back to SMII_RCOMP_CSR
register.
4. Write the EXP_SMIIDLL register to enable the DLL.
5. Write the Expansion EXP_CNFG1 register to turn on SMII mode for the appropriate NPE's (SMII
mode for NPE-B must be enabled for SMII mode to work on NPE-A or NPE-C)
6. Read the Expansion EXP_CNFG1 register to ensure previous write has occurred
7. Wait at least 1000 ns
8. Write the Expansion EXP_UNIT_FUSE_RESET register to turn OFF the reset for the NPE's.
9. Resume normal boot-up
10. Wait at least 12ms before starting Ethernet traffic on ports that have SMII enabled, since it takes 12
ms for the SMII pins to stabilize.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Name
0 = MII mode enabled for NPE-C
1 = SMII mode enabled for NPE-C
NPE-C SMII
This bit must be configured during boot-up and cannot change
unless a system reset is performed.
Note:
0 = MII mode enabled for NPE-B
1 = SMII mode enabled for NPE-B
Refer to
NPE-B SMII
This bit must be configured during boot-up and cannot change
unless a system reset is performed
Note:
0 = MII mode enabled for NPE-A
1 = SMII mode enabled for NPE-A
NPE-A SMII
This bit must be configured during boot-up and cannot change
unless a system reset is performed.
Note:
(Reserved) (Reserved)
0 = Error handling in NPE-C is disabled
NPE-C ERR_EN
1 = Error handling in NPE-C is enabled. For more information, see
"Error Handling" on page
0 = Error handling in NPE-B is disabled
NPE-B ERR_EN
1 = Error handling in NPE-B is enabled. For more information, see
"Error Handling" on page
0 = Error handling in NPE-A is disabled
NPE-A ERR_EN
1 = Error handling in NPE-A is enabled. For more information, see
"Error Handling" on page
(Reserved) (Reserved)
Intel
Description
See note, below.
Table 233 for more details.
See note, below.
See note, below.
951.
951.
951.
®
Processor, the selection between address or data
®
IXP425 processor.
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
IXP4XX Product
Developer's Manual
711