Intel IXP45X Developer's Manual page 718

Register
Bits Name
The register specifies the upper AHB address used for inbound
31:2 transfers. Bits 31:24 of the AHB address reflect this register setting.
BaseAddr
1 Bits 23:21 of the AHB address are dependent on the value of
AddrWidth. See description under AddrWidth.
20:4 Reserved Reserved
The value represents which bits of the BaseAddr should be used for
the calculation of the AHB address on inbound transfers.
0x8: AHB ADDR = BaseAddr[31:24] & EX_ADDR[23:0] when
EX_ADDR[24] = '0'
0x9: AHB ADDR = BaseAddr[31:23] & EX_ADDR[22:0] when
EX_ADDR[23] = '0'
3:0 AddrWidth
0xA: AHB ADDR = BaseAddr[31:22] & EX_ADDR[21:0] when
EX_ADDR[22] = '0'
0xB: AHB ADDR = BaseAddr[31:21] & EX_ADDR[20:0] when
EX_ADDR[21] = '0'
others: Reserved
TT
Note: The BaseAddr must not be programmed to loop back to the Expansion Bus controller
address space or Expansion Bus controller MMR space and results in unpredictable
operation if programmed for loopback. Additionally, the Expansion bus controller does
not support inbound accesses to the AHB Queue Manager SRAM. Accesses to the AHB
Queue Manager queue's are allowed, however they must be 1-word accesses. Another
restriction that must be followed is that if the BaseAddr is programmed to target the
PCI Controller, the PCI controller cannot be programmed to access the Expansion bus
at the same time. If simultaneous PCI to Expansion bus traffic and Expansion bus to
PCI traffic is desired, there are two methods to support this.
1. Program the PCI Controller to transfer the data to main memory and then use the
Intel XScale processor to transfer the data from main memory to the Expansion
bus.
2. If there is PCI to Expansion bus traffic, ensure that there is never Expansion bus to
PCI traffic until the PCI to Expansion bus traffic is complete.
The EXP_INBOUND_ADDR register can be read/written from the AHB bus and from an
external master. This allows an external master to re-configure the BaseAddr if ExtCfg
is clear. External masters must be careful not to program AddrWidth to an unintended
value. External masters accesses to the EXP_INBOUND_ADDR register is only
supported for word accesses. Sub-word accesses will be treated as a word access.
Additionally, the EXP_BYTE_SWAP_EN is ignored for accesses to the
EXP_INBOUND_ADDR register. Simultaneous writing of the EXP_INBOUND_ADDR
register from the AHB and an external master results in unpredictable operation. If
ExtCfg is set, external master reads to EXP_INBOUND_ADDR are supported, but writes
are ignored. The Expansion bus controller uses the appropriate EX_ADDR bit to
determine if the Expansion bus access targets an Expansion bus MMR or the AHB bus.
If the most significant EX_ADDR bit (which is based upon AddrWidth) is a '1', the
access will target the externally visible Expansion bus MMRs.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
718
® ®
Intel IXP45X and Intel
Description
IXP46X Product Line of Network Processors—Expansion Bus
EXP_INBOUND_ADDR
Controller
Reset
Access
Value
0x0 RW
0x0 RO
0x8 RW
August 2006
Order Number: 306262-004US