Out Packet Ready (Opr); Flush Tx Fifo (Ftf); In Packet Ready (Ipr); Device Remote Wake-Up Feature (Drwf) - Intel IXP45X Developer's Manual

8.5.2.1

OUT Packet Ready (OPR)

The OUT packet ready bit is set by the UDC when it receives a valid OUT packet to
endpoint 0. When this bit is set, the USIR0[IR0] bit will be set in the UDC status/
interrupt register if endpoint zero interrupts are enabled. This bit is cleared by writing a
1. The UDC is not allowed to enter the data phase of a transaction until this bit is
cleared.
8.5.2.2

IN Packet Ready (IPR)

The IN packet ready bit is set by the Intel XScale processor if less than max_packet
bytes (16) have been written to the endpoint 0 FIFO to be transmitted. The Intel
XScale processor must not set this bit if a max_packet is to be transmitted. The UDC
clears this bit when the packet has been successfully transmitted, the UDCCS0[FTF] bit
has been set, or a control OUT is received. When this bit is cleared due to a successful
IN transmission or the reception of a control OUT, the USIR0[IR0] bit in the UDC
interrupt register is set if the endpoint 0 interrupt is enabled via UICR0[IM0]. The Intel
XScale processor is not able to clear UDCCS0[IPR] and always reads back a 0.
When software enables the status stage for Vendor/Class commands and control data
commands such as GET_DESCRIPTOR, GET_CONFIGURATION, GET_INTERFACE,
GET_STATUS, and SET_DECSCRIPTOR, software must also set IPR. The data in the
Transmit FIFO must be transmitted and the interrupt must be processed before the IPR
is set for the status stage.
The status stage for all other USB Standard Commands that do not have a data stage,
such as SET_ADDRESS, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and
CLEAR_FEATURE, is handled by the UDC and the software must not set IPR.
8.5.2.3

Flush Tx FIFO (FTF)

The Flush Tx FIFO bit triggers the reset of the endpoint 0 transmit FIFO. It is set when
software writing a 1 or when the UDC receives an OUT packet from the host on
endpoint 0. This bit always reads back a 0 value.
8.5.2.4

Device Remote Wake-Up Feature (DRWF)

The host indicates the state of the device remote wake-up feature by sending a Set
Feature command or a Clear Function command. The UDC decodes the command sent
by the host and sets this bit to a 1 if the feature is enabled and a 0 if the feature is
disabled.
This bit is read-only.
8.5.2.5

Sent Stall (SST)

The sent stall bit is set by the UDC when FST successfully forces a software-induced
STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from
the host when a STALL handshake is returned automatically. In this event, there is no
intervention by the Intel XScale processor and the UDC clears the STALL status before
the host sends the next SETUP command.
When the UDC sets this bit, the transmit FIFO is flushed. The Intel XScale processor
writes a 1 to this bit to clear it.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
294
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
August 2006
Order Number: 306262-004US