Event Select Registers - Intel IXP45X Developer's Manual

Intel
16.6.1

Event Select Registers

The ESR controls the specific item being monitored. Each PECx field is programmed
according to
To change the monitored event, it is necessary to write the entire ESR. The
Programmable Event Counters are reset and started when a new value is written to the
ESR. However, notice that since there are two registers and one cannot write both of
them in the same cycle, it is preferable to halt the counters via the MODE register (i.e.,
PMR), update the mux selects via these registers (which will reset the counters), and
then enable the desired counters with the PMR.
Register Name:
Physical Address:
Register Description:
Access: Read/Write
PEC3 ctrl
Register
Bits Name
31:2
PEC3 ctrl Selects Enable conditions for counter PEC3.
4
23:1
PEC2 ctrl Selects Enable conditions for counter PEC2.
6
15:8 PEC1 ctrl Selects Enable conditions for counter PEC1.
7:0 PEC0 ctrl Selects Enable conditions for counter PEC0.
Register Name:
Physical Address:
Register Description:
Access: Read/Write
PEC7 ctrl
Register
Bits Name
31:2
PEC7 ctrl Selects Enable conditions for counter PEC7.
4
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
794
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring
Table 260, "Event Mux Programming" on page
0xC800 2000
Event Mux Select Register, counters 3-0
PEC2 ctrl
Description
0xC800 2004
Event Mux Select Register, counters 7-4
PEC6 ctrl
Description
ESR0
Reset Hex Value:
PEC1 ctrl
ESR
ESR1
Reset Hex Value:
PEC5 ctrl
ESR (Sheet 1 of 2)
Unit (PMU)
ESR0 and ESR1
799.
0x00000000
PEC0 ctrl
Reset
Access
Value
0xFF RW
0xFF RW
0xFF RW
0xFF RW
0x00000000
PEC4 ctrl
Reset
Access
Value
0xFF RW
August 2006
Order Number: 306262-004US