Queue Control - Intel IXP45X Developer's Manual

AHB Queue Manager (AQM)—Intel
Processors
Table 293. AHB Queue Manager Memory Map (Sheet 2 of 2)
0x0043C
0x00438
0x00434
0x00430
0x0042C
0x00420
0x0041C
0x00418
0x00414
0x00410
0x0040C
0x00400
0x003FC
0x00000
27.4.1

Queue Control

The queues are implemented as circular buffers where adding an entry is performed by
a write to a queue and removing an entry is performed by a read from a queue. Entries
are read from a queue in the same order in which they were written to the queue. The
read/write pointers track the removal/addition of entries from/to a queue. The queue
control performs the autonomous access of the queues. External agents wanting to
access a queue, will perform an AHB read or write to the Queue Access Register
locations. As a result of the access to these locations, the AQM will perform the
requested access to the queue in SRAM. Support is provided for 64 queues. Upon
receiving a queue read or queue write from the AHB interface, queue control fetches
the selected queue configuration from SRAM. The queues or circular buffers will reside
in internal SRAM. Configuration for each queue will consists of:
• A Base Address — The address where the queue starts and is configurable for
placing the queue buffer on any 16 word boundary within the SRAM address range
of 000H to 7C0H (word address). These SRAM address ranges correspond to AQM
address ranges 0x2000 to 0x3FFC respectively. Note that the lower SRAM
addresses are used to store the queue control words and therefore should not be
used for queue data storage.
• A Write Pointer — A pointer to the next queue location to be written and is
maintained by queue control.
• A Read Pointer — A pointer to the next location to be read and is maintained by
queue control.
• Queue Entry Size — The size of each queue entry. This is configurable for 1, 2, or 4
words.
• Queue Size — The number of words allocated to the queue and is configurable for
16, 32, 64, or 128 words.
— Examples of how to use the Queue Entry Size and Queue Size parameters to
August 2006
Reference Number: 306262-004US
®
IXP45X and Intel
Queue 0 to 63 Interrupt Enable Register
Queue 0 to 31 Interrupt Status Flag Source Select Register
Queue 32 to 63 Full Status Register
Queue 32 to 63 Nearly Empty Status Register
Queue 0 to 31 Underflow/Overflow Status Register
obtain number of Q-entries for each of the 64 queues when program a Q-
Manager size of 8KB
®
IXP46X Product Line of Network
Queue 0 to 63 Interrupt Register
2 x 4 Bytes
2 x 4 Bytes
4 x 4 Bytes
2 x 4 Bytes
Queue 0 to 31 Status Registers
4 x 4 bytes
Queue 0 to 63 Read/Write Access
64 x 16 bytes
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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