Ssp Interrupt Test Register (Ssitr); Ssp Data Register (Ssdr) - Intel IXP45X Developer's Manual

Intel
Register
Bits Name
SSP is busy
4 BSY
0 = SSP is idle or disabled
1 = SSP currently transmitting or receiving a frame
Receive FIFO not empty.
3 RNE 0 - Receive FIFO is empty
1 - Receive FIFO is not empty
Transmit FIFO not Full.
2 TNF
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
1:0 (Reserved) (Reserved)
20.5.4

SSP Interrupt Test Register (SSITR)

Writing "1" to the corresponding bit position to the SSP Interrupt Test register
generates an interrupt strobe signal to the Interrupt Controller or a DMA request for
test purposes.
Note: SSITR functionality is available even when the SSP is disabled.
Register Name:
Block
0xC801_20
Base Address:
SSP Interrupt Test Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:08 (Reserved) (Reserved)
7 TROR Test Receive FIFO overrun (ROR)
6 TRFS Test Receive FIFO service request (RFS)
5 TTFS Test Transmit FIFO service request (TFS)
4:0 (Reserved) (Reserved)
20.5.5

SSP Data Register (SSDR)

The SSP Data Register (SSDR) is a block of 32-bit locations that can be accessed by 32-
bit data transfers. The SSDR represents two physical registers: the first is temporary
storage for data on its way out through the Transmit FIFO, the other is temporary
storage for data coming in through the Receive FIFO.
As the register is accessed by the system, FIFO control logic transfers data
automatically between register and FIFO as fast as the system moves it. Data in the
FIFO shifts up or down to accommodate the new word (unless it is an attempted WRITE
to a full Transmit FIFO). Status bits are available to show the system whether either
buffer is full, above/below a programmable threshold, or empty.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
872
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port
Description
Offset Address
Reserved
Description
SSSR (Sheet 2 of 2)
SSITR
0x0C
8
SSITR
Reset Value Access
0 RO
0 RO
1 RO
00 RV
0x0000_0000
Reset Value
Access: (See below.)
7 6 5 4 3 2 1
Reserved
Reset Value Access
0x0000 RV
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RV
August 2006
Order Number: 306262-004US
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