Eight-Word Inbound Read With Deassertion Of Ex_Slave_Cs_N; Expansion Bus Arbiter Timing Diagrams; Arbitration When Grantremove Bit In Exp_Mst_Control Is Set - Intel IXP45X Developer's Manual

12.4.5.11

Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N

Figure 160. Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N
- 0 - - 1 -
EX_CLK
EX_ IXPCS_N
EX_ ADDR
ADDR0
EX_RD_N
EX_WR_N
EX_BE_N
EX_ BURST
EX_ WAIT_N
EX_ DATA
EX_ PARITY
STATE
IDLE NOP
The above timing diagram shows an external master choosing to deassert
EX_SLAVE_CS_N after the 1st word is transferred. The external master resumes the
burst in cycle 6 and the Expansion bus controller does not assert EX_WAIT_N, since
EX_ADDR[4:2] does not equal 0x0.
12.4.6

Expansion Bus Arbiter Timing Diagrams

12.4.6.1 Arbitration When GrantRemove Bit In EXP_MST_CONTROL
is Set
Figure 161. Arbitration When GrantRemove Bit In EXP_MST_CONTROL is Set
- 0 -
EX_CLK
EX_CS_N/
EX_IXPCS _N
EXPANSION BUS
OUTPUTS
EX_REQ0_ IXPGNT _N
EX_GNT0_ IXPREQ _N
EX_REQ _N[1]
EX_GNT _N[1]
STATE
ARBITRATE
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
698
®
Intel IXP45X and Intel
- 3 - - 4 - - 5 -
- 2 -
DATA0
PAR0
WAIT DATA0
- 1 - - 2 - - 3 -
GNT MST0
®
IXP46X Product Line of Network Processors—Expansion Bus
- 6 - - 7 - - 8 - - 9 -
ADDR1 ADDR2
DATA1 DATA1
PAR1
IDLE DATA1 DATAX DATA2
- 4 - - 5 - - 6 -
- 10 - - 11 - - 12 -
ADDR7
DATA7
PAR1 PAR7
DATAX DATA7
- 7 - - 8 - - 9 - - 10 -
Arbiter monitors
EX_CS_N/EX_IXPCS_N
before asserting
EX_GNT_N[1]
_
ARBITRATE GNT MST1
August 2006
Order Number: 306262-004US
Controller
- 13 -
IDLE
B4458-01
B4461-01