Mcu Active, Precharge, Refresh Command Timing Diagram - Intel IXP45X Developer's Manual

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Memory Controller—Intel
Figure 110. MCU Active, Precharge, Refresh Command Timing Diagram
t0
tn
m_clk
A
ACT
tRC
PCH
t
RAS
t
RCD
ARF
t
RFC
PCH CMD
t
RP
The timing parameters for DDR reads are defined in
(IXP45X/IXP46X network processors t
network processors t
remain separate for two reasons: 1) For similarity to the DDR Write timing parameters,
and 2) to allow for flexibility in programming the MCU that might not have been
comprehended at the time of its design. Both parameters take into account CAS latency
(JEDEC: t
Note: Burst Length is fixed at four for the IXP45X/IXP46X network processors.
Note: The MCU allows for back-to-back reads, so long as they are to a currently open page.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
tn+1 tn+3
tn+2 tn+4
A/A
ACT or ARF
Read or Write
R/W
ACT or ARF
A/A
Next command
) are defined the same. It is important to note that they
RTCMD
) and Burst Length (JEDEC: BL).
CAS
Notes:
t
= Active to Active, Active to Refresh
RC
t
= Refresh to Active, Refresh to Refresh
RFC
t
= Precharge Command Period
RP
t
= Active to Precharge
RAS
t
= Active to Read, Active to Write
RCD
Figure
) and Read to Command (IXP45X/IXP46X
RTW
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
B4215-001
111. Both Read to Write
Developer's Manual
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