Byte Lane Routing During Dma Transfers - Intel IXP45X Developer's Manual

Figure 99.

Byte Lane Routing During DMA Transfers

31
24
PCI Data
3
31 24 23
AHB Data
31
24
PCI Data
3
31 24 23
AHB Data
There is no byte lane reversal for accesses to PCI Controller CSRs or PCI Configuration
registers.
CSR write with byte enable 2 asserted, for example, will write to bits 23:16 of the
register. An AHB write with Address bits [1:0] = 10b in big-endian mode (pci_csr.ABE =
1) will write bits 15:8 of the register. In little-endian mode (pci_csr.ABE = 0), bits
23:16 will be written.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
546
®
Intel IXP45X and Intel
AHB-to-PCI DMA,
DS = 1
23 16 15 7
8 0
2 0
1
16 15 7
8 0
AHB-to-PCI DMA,
DS = 0
23 16 15 7
8 0
2 0
1
16 15 7
8 0
Figure 100 shows the byte lane routing for these types of accesses. A PCI
®
IXP46X Product Line of Network Processors—PCI Controller
31 24
PCI Data
3
31 24 23
AHB Data
31 24
PCI Data
3
31 24 23
AHB Data
PCI-to-AHB DMA,
DS = 1
23 16 15 8 7 0
2 1 0
16 15 8 7 0
PCI-to-AHB DMA,
DS = 0
23 16 15 8 7 0
2 1 0
16 15 8 7 0
B4303-01
August 2006
Order Number: 306262-004US