Modes Of Operation - Intel IXP45X Developer's Manual

Intel
also be used instead of interrupts, although it would be very cumbersome.
on page 876
the internal bus.
2
The I C Bus Interface Unit consists of the two wire interface to the I
buffer for passing data to and from the processor, a set of control and status registers,
and a shift register for parallel/serial conversions.
2
The I C Bus Interface Unit can initiate an interrupt when a buffer is full, buffer empty,
slave address detected, arbitration lost, or bus error condition occurs. All interrupt
conditions must be cleared explicitly by software. See
page 899
2
The I C Data Buffer Register (IDBR) is an 8-bit data buffer that receives a byte of data
from the shift register interface of the I
processor's internal bus on the other side. The serial shift register is not user
accessible.
The control and status registers are located in the I
The registers and their function are defined in
2
The I C Bus Interface Unit supports fast mode operation of 400 Kbps. Fast-mode logic
levels, formats, and capacitive loading, and protocols are exactly the same as the
100 Kbps, standard mode. Because the data setup and hold times differ between the
fast and standard mode, the I
requirements for these two specifications. Refer to the I
2
21.4.2 I C Bus Interface Modes
2
The I C Bus Interface Unit can be in different modes of operation to accomplish a
transfer.
Table 277.

Modes of Operation

Master - Transmit
Master - Receive
Slave - Transmit
Slave - Receive (default)
While the I
data), the unit defaults to Slave-Receive mode. This allows the interface to monitor the
bus and receive any slave addresses that might be intended for the IXP45X/IXP46X
network processors.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
878
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
shows a block diagram of the I
for details.
2
C has been designed to meet the faster, standard mode
Table 277 summarizes the different modes.
Mode
2
I C Bus Interface Unit acts as a master.
Used for a write operation.
2
I C Bus Interface Unit sends the data.
2
I C Bus Interface Unit is responsible for clocking.
Slave device will be in slave-receive mode
2
I C Bus Interface Unit acts as a master.
Used for a read operation.
2
I C Bus Interface Unit receives the data.
2
I C Bus Interface Unit is responsible for clocking.
Slave device will be in slave-transmit mode
2
I C Bus Interface Unit acts as a slave.
Used for a read (master) operation.
2
I C Bus Interface Unit sends the data.
Master device will be in master-receive mode.
2
I C Bus Interface Unit acts as a slave.
Used for a write (master) operation.
2
I C Bus Interface Unit receives the data.
Master device will be in master-transmit mode.
2
C Bus Interface Unit is in idle mode (neither receiving or transmitting serial
2
C Bus Interface Unit and its interface to
"I2C Status Register - ISR" on
2
C bus on one side and parallel data from the
2
C memory-mapped address space.
"Register Definitions" on page
2
C Bus Specification for details.
Definition
Figure 190
2
C bus, an 8-bit
896.
August 2006
Order Number: 306262-004US