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• Over-current Change bits are set to a one. On every transition of the Over-current
Active bit the host controller will set the Over-current Change bit to a one. Software
sets the Over-current Change bit to a zero by writing a one to this bit.
• Port Enabled/Disabled bit is set to a zero. When this change bit gets set to a one,
then the Port Change Detect bit in the USBSTS register is set to a one.
• Port Power (PP) bits may optionally be set to a zero. There is no requirement in
USB that a power provider shut off power in an over current condition. It is
sufficient to limit the current and leave power applied. When the Over-current
Change bit transitions from a zero to a one, the host controller also sets the Port
Change Detect bit in the USBSTS register to a one. In addition, if the Port Change
Interrupt Enable bit in the USBINTR register is a one, then the host controller will
issue an interrupt to the system. Refer to
Events" on page 418
host controller is halted (suspended from a device component point of view).
9.14.3
Suspend/Resume
The EHCI host controller provides an equivalent suspend and resume model as that
defined for individual ports in a USB 2.0 hub. Control mechanisms are provided to allow
system software to suspend and resume individual ports. The mechanisms allow the
individual ports to be resumed completely via software initiation. Other control
mechanisms are provided to parameterize the host controller's response (or sensitivity)
to external resume events. In this discussion, host-initiated, or software initiated
resumes are called Resume Events/Actions. Bus-initiated resume events are called
wake-up events. The classes of wake-up events are:
• Remote-wakeup enabled device asserts resume signaling. In similar kind to USB
2.0 hubs, EHCI controllers must always respond to explicit device resume signaling
and wake up the system (if necessary).
• Port connect and disconnect and over-current events. Sensitivity to these events
can be turned on or off by using the per-port control bits in the PORTSC registers.
Selective suspend is a feature supported by every PORTSC register. It is used to place
specific ports into a suspend mode. This feature is used as a functional component for
implementing the appropriate power management policy implemented in a particular
operating system. When system software intends to suspend the entire bus, it should
selectively suspend all enabled ports, then shut off the host controller by setting the
Run/Stop bit in the USBCMD register to a zero. The EHCI module can then be placed
into a lower device state.
When a wake event occurs the system will resume operation and system software will
eventually set the Run/Stop bit to a one and resume the suspended ports. Software
must not set the Run/Stop bit to a one until it is confirmed that the clock to the host
controller is stable. This is usually confirmed in a system implementation in that all of
the clocks in the system are stable before the CPU is restarted. So, by definition, if
software is running, clocks in the system are stable and the Run/Stop bit in the
USBCMD register can be set to a one.
9.14.3.1
Port Suspend/Resume
System software places individual ports into suspend mode by writing a one into the
appropriate PORTSC Suspend bit. Software must only set the Suspend bit when the
port is in the enabled state (Port Enabled bit is a one) and the EHCI is the port owner
(Port Owner bit is a zero).
The host controller may evaluate the Suspend bit immediately or wait until a micro-
frame or frame boundary occurs. If evaluated immediately, the port is not suspended
until the current transaction (if one is executing) completes. Therefore, there may be
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
416
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—USB 2.0 Host Controller
for summary behavior for over-current detection when the
Table 170, "Behavior During Wake-Up
Order Number: 306262-004US
August 2006
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