Intel IXP45X Developer's Manual page 21

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Contents-Intel IXP45X and Intel
17.6.5 FIQ Status Register .............................................................................. 814
17.6.6 Interrupt Priority Register...................................................................... 815
17.6.7 IRQ Highest-Priority Register ................................................................. 815
17.6.8 FIQ Highest-Priority Register.................................................................. 816
17.6.9 Error High Priority Enable Register .......................................................... 816
18.0 Operating System Timer ........................................................................................ 817
18.1 Overview ....................................................................................................... 817
18.2 Feature List .................................................................................................... 817
18.3 Block Diagram ................................................................................................ 817
18.4 Theory of Operation......................................................................................... 818
18.4.1 Watchdog Timer Operation .................................................................... 818
18.4.2 Timestamp Timer Operation................................................................... 819
18.4.3 General-Purpose Timers Operation ......................................................... 820
18.4.4 Clock Prescale...................................................................................... 821
18.5 Detailed Register Descriptions........................................................................... 821
18.5.1 Timestamp Timer ................................................................................. 822
18.5.2 General-Purpose Timer 0....................................................................... 822
18.5.3 General-Purpose Timer 0 Reload ............................................................ 823
18.5.4 General-Purpose Timer 1....................................................................... 823
18.5.5 General-Purpose Timer 1 Reload ............................................................ 824
18.5.6 Watchdog Timer................................................................................... 824
18.5.7 Watchdog Enable Register ..................................................................... 825
18.5.8 Watchdog Key Register ......................................................................... 825
18.5.9 Timer Status........................................................................................ 826
18.5.10Timestamp Compare Register ................................................................ 826
18.5.11Timestamp Configuration Register .......................................................... 827
18.5.12Timestamp Prescale Register ................................................................. 827
18.5.13General-Purpose Timer 0 Configuration Register ....................................... 828
18.5.14General-Purpose Timer 0 Prescale Register .............................................. 828
18.5.15General-Purpose Timer 1 Configuration Register ....................................... 829
18.5.16General-Purpose Timer 1 Prescale Register .............................................. 829
19.0 Time Synchronization Hardware Assist (TSYNC) .................................................... 830
19.1 Overview ....................................................................................................... 830
19.2 Block Diagram ................................................................................................ 830
19.3 Theory of Operation (Ethernet Interfaces) .......................................................... 831
19.3.1 Priority Message Support....................................................................... 832
19.3.2 Sync Message ...................................................................................... 832
19.3.3 Follow_Up Message .............................................................................. 832
19.3.4 Delay_Req Message.............................................................................. 833
19.3.5 Delay_Resp Message ............................................................................ 833
19.3.6 IPv6 Compatibility ................................................................................ 833
19.3.7 Traffic Analyzer Support ........................................................................ 833
19.3.8 MII Clocking Methods............................................................................ 833
19.3.9 System Time Clock Rate Set by Addend Register ...................................... 833
19.3.10MII Message Detection .......................................................................... 834
19.3.10.1Sync Message ........................................................................ 835
19.3.10.2Delay_Req Message ................................................................ 835
19.3.10.3Errors in Messages .................................................................. 835
19.4 Theory of Operation (Auxiliary Snapshots) .......................................................... 836
19.4.1 Master Mode Programming Considerations ............................................... 836
19.4.2 Slave Mode Programming Considerations................................................. 836
19.5 Detailed Register Descriptions........................................................................... 836
19.5.1 Register Map ....................................................................................... 836
19.5.2 Register Descriptions ............................................................................ 838
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
21