Super Pipeline; Processor Block Diagram; Bus - Intel IXP45X Developer's Manual

Intel
Figure 4. Intel XScale
Coprocessor Interface
2.2.1

Super Pipeline

The super pipeline is composed of integer, multiply-accumulate (MAC), and memory
pipes.
The integer pipe has seven stages:
• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
• Integer Writeback
The memory pipe has eight stages:
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
. . . then finish with the following memory stages
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
The MAC pipe has six to nine stages:
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview
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Processor Block Diagram

FIQ
Interrupt
IRQ
Request
Instruction
Execution
Core
Address
Multiply System
Accumulate Management
Branch Target Cache
Instruction Cache
32Kb
Data Cache
Data
32Kb
Mini-Data Cache
Data
2Kb
Debug/
PMU
JTAG
M
M
U
South
AHB

Bus

M
M
U
B4571-01
August 2006
Reference Number: 306262-004US