Memory Controller Block Diagram; Transaction Ports - Intel IXP45X Developer's Manual

Figure 101. Memory Controller Block Diagram
Address
Decode
11.2.1.1

Transaction Ports

The MCU provides three transaction ports for DDRI SDRAM access. They consist of two
Internal Bus ports (AHB ports for the north and south AHB buses) and a direct port
from the BIU (Core Processor Port):
11.2.1.1.1 Core Processor Port (From BIU)
The Core Processor Port provides a direct connection between the core bus interface of
the IXP45X/IXP46X network processors and the Memory Controller. This Core Processor
Port allows core transactions targeting the DDRI SDRAM to pass directly to the DDRI
SDRAM.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
584
® ®
Intel IXP45X and Intel
®
Intel XScale
Processor
Core Memory
Bus (CMB)
BIU Unit
MCU
Core Memory
Port Interface
MPI Bus
Queues
(IBMTQ)
AHB South BUS
AHB South Bus
IXP46X Product Line of Network Processors—Memory Controller
MCU Core
MARB
Arbiter
MAB - AHB to MPI Bridge/
Gasket
MCU
Internal
Bus Ports
MCU Unit
DDR
DDR
Control
Interface
Block
AHB North BUS
AHB North Bus
B3968 -002
August 2006
Order Number: 306262-004US