Udc Endpoint 5 Control/Status Register; Transmit Fifo Service (Tfs); August - Intel IXP45X Developer's Manual

Register Name:
0x C800B020
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 4 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.7

UDC Endpoint 5 Control/Status Register

The UDC Endpoint 5 Control Status Register contains six bits that are used to operate
Endpoint 5, an Interrupt IN endpoint.
8.5.7.1

Transmit FIFO Service (TFS)

The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS5[TSP] is not set.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Receive short packet (read only).
RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
RNE 0 = Receive FIFO empty.
1 = Receive FIFO not empty.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
(Reserved)
Receive overflow (read/write 1 to clear).
ROF
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
Receive packet complete (read/write 1 to clear).
RPC 0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS 0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS4
0x00000000
Reset Hex Value:
Bits
UDCCS4
Description
Controller
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0
(UDCCS5)

August 2006

Order Number: 306262-004US
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