Interrupt Controller Block Diagram - Intel IXP45X Developer's Manual

Intel
• Standard AMBA APB Interface clocked from qualified pclk.
17.3 Block Diagram
This is the top level block diagram for a module. It typically shows the inputs, outputs
and major internal blocks.
Figure 186. Interrupt Controller Block Diagram
intr_bus[63:0]
hclk
psuedo_pclk
(apb_ahb_en)
brg_pwrite
brg_pwdata[31:0]
brg_preset_n
brg_apddr[8:2]
brg_psel_intr
brg_penable
17.4 Theory of Operation
The Interrupt Controller takes as inputs 63 individual interrupts (with interrupt 64
reserved). These 63 individual interrupts originate either from internal blocks on the
IXP45X/IXP46X network processors or from dedicated GPIO pins. Interrupts are
asserted if set ('1') and de-asserted if reset ('0').
There are two classes of interrupts, both of which are defined by their positional priority
(e.g position 12 is of higher priority than position 42). The "error" class of interrupts
have unconditional priority over "normal" (i.e. not "error" class). The Interrupt Error
Enable Register is a 32-bit register that assigns each of the [63:32] interrupts to be the
special error interrupts.
For the "normal" class, the highest positional priority interrupt is bit [0] assigned to the
NPE A interrupt and the lowest priority interrupt (of the first group) is bit [31] assigned
to a Software Interrupt. Interrupts [63:32] are lower priority than the Software
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
806
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Interrupt Controller
Interrupt
Priority
Generation
APB
Interface /
Control
Registers
Interrupt
Controller
Interrupt
Status
Register
APB
Read
Mux
Reference Number: 306262-004US
intr_fiq
intr_irq
intr_prdata[31:0]
B4274-01
August 2006