Sof Interrupt; Embedded Design Interface; Frame Adjust Register; Miscellaneous Variations From Ehci - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
9.15.2.3

SOF Interrupt

This SOF Interrupt used for device mode is shared as a free-running, 125-us interrupt
for host mode. EHCI does not specify this interrupt but it has been added for
convenience and as a potential software time base. See
page 375
9.15.3

Embedded Design Interface

This is an Embedded USB Host Controller as defined by the EHCI specification and thus
does not implement the PCI configuration registers.
9.15.3.1

Frame Adjust Register

Given that the optional PCI configuration registers are not included in this
implementation, there is no corresponding bit level timing adjustments like is provided
by the Frame Adjust register in the PCI configuration registers. Starts of micro-frames
are timed precisely to 125 us using the transceiver clock as a reference clock. For
example, using a 60-MHz transceiver clock for 8-bit physical interfaces and full-speed
serial interfaces or using a 30-MHz transceiver clock for 16-bit physical interfaces.
9.15.4

Miscellaneous Variations from EHCI

9.15.4.1

Programmable Physical Interface Behavior

This design supports multiple Physical interfaces which can operate in differing modes
when the core is configured with software programmable Physical Interface Modes. See
Configuration Constants. Software programmability allows the selection of the Physical
interface part during the board design phase instead of during the chip design phase.
The control bits for selecting the Physical Interface operating mode have been added to
the PORTSCx register providing a capability that is not defined by EHCI.
9.15.4.2

Discovery

9.15.4.2.1 Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the
PORTSCx register for a duration of 10ms. Due to the complexity required to support the
attachment of devices that are not high speed there are counter already present in the
design that can count the 10ms reset pulse to alleviate the requirement of the software
to measure this duration. Therefore, the basic connection is then summarized as the
following:
• [Port Change Interrupt] Port connect change occurs to notify the host controller
driver that a device has attached.
• Software will write a '1' to the reset the device.
• Software will write a '0' to the reset the device after 10 ms.
— This step, which is necessary in a standard EHCI design, may be omitted with
• [Port Change Interrupt] Port enable change occurs to notify the host controller that
the device in now operational and at this point the port speed has been
determined.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
and Section 9.12.3, "USBINTR" on page
this implementation. Should the EHCI host controller driver attempt to write a
'0' to the reset bit while a reset is in progress the write will simple be ignored
and the reset will continue until completion.
377.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Section 9.12.2, "USBSTS" on
Developer's Manual
491