Configuration Registers; Memory Transaction Queues; Refresh Counter - Intel IXP45X Developer's Manual

Space, the transaction is queued in the Internal Bus Port Transaction Queue. If the
transaction addresses the MCU MMR Space, the transaction is serviced by accessing the
Configuration Register block.
11.2.1.3

Memory Transaction Queues

There are two transaction queues for transactions which address the MCU DDRI
Memory Space. One transaction queue is for Core Processor transactions and one
transaction queue is for Internal Bus transactions (North and South AHB).
11.2.1.3.1 Core Processor Memory Transaction Queue (CMTQ)
The CMTQ stores memory transactions from the core which have not been processed
by the Memory Controller. The CMTQ supports 8 Core Processor posted write
transactions up to 16-Bytes each. The CMTQ also supports eight Core Processor read
transactions up to 32 Bytes each, which equals the maximum number of outstanding
transactions the Intel XScale
eight read transactions are:
• core DCU: 4 load requests to unique cachelines
• IFU: 2 - prefetch
• IMM: 1 - tablewalk
• DMM: 1 - tablewalk
11.2.1.3.2 AHB Internal Bus Memory Transaction Queue (IBMTQ)
Each IBMTQ stores memory transactions from the Internal Buses that address the
DDRI SDRAM Memory Space. Each IBMTQ can hold 2 outstanding Internal Bus read or
write transaction requests. The read transactions are processed one at a time, each
with up to 32-Bytes of read data. The IBMTQ also supports 2 posted write transactions
up to 32 Bytes each.
Note: The MCU Internal Bus Port will not split or retry Internal Bus Read Transactions. Instead
it will stay on the bus until the read data is returned from the DRAM. This enables the
queuing of outstanding read transactions without modifying the existing peripheral
units of the IXP45X/IXP46X network processors. Internal Bus Write Transactions will be
posted to improve bus bandwidth.
11.2.1.4

Configuration Registers

The Configuration Registers block contains all of the memory-mapped registers listed in
Section 11.6, "Register
connected to the IXP45X/IXP46X network processors. The status registers indicate the
current MCU status.
11.2.1.5

Refresh Counter

The Refresh Counter block keeps track of when the DDRI SDRAM devices need to be
refreshed. The refresh interval is programmed in the
Frequency Register
interval, the DDRI SDRAM state machine issues a refresh command to the DDRI
SDRAM devices. If a transaction is currently in progress, the DDRI SDRAM State
Machine waits for the completion of the transaction to issue the refresh cycle. See
Section 11.2.2.12, "DDRI SDRAM Refresh Cycle"
Note: If the memory interface is busy when the refresh counter expires, it is possible for the
MCU to generate more than one refresh cycle when the memory interface becomes
available.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
586
® ®
Intel IXP45X and Intel
®
Processor Processor Bus Controller can support. The
Definitions". These registers define the memory subsystem
RFR". Once the 12-bit refresh counter reaches the programmed
IXP46X Product Line of Network Processors—Memory Controller
Section 11.6.14, "Refresh
for more details.
August 2006
Order Number: 306262-004US