Pci Initiator Interface Supported Commands - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
— Interrupt Acknowledge, Special Cycle, I/O, Configuration, and single-data-
For PCI bus memory cycles, the PCI Initiator interface will receive requests for PCI
transfer from the PCI Controller DMA channels. For PCI bus I/O cycles and configuration
cycles, the PCI Initiator interface will receive requests for PCI transfer from an AHB
master (a single word PCI Bus Memory Cycle can be produced using this method).
Requests for PCI transfers using the PCI Controller Initiator interface are buffered in
the Initiator Request FIFO and handled by the PCI Controller Initiator interface when
appropriate. The Initiator interface will receive the appropriate transfer information
from the Initiator Request FIFO; which is the address, word count, byte enables, and
PCI command type.
The Initiator Request FIFO is a four-entry FIFO allowing up to four requests to be
buffered. If a request is issued that generates an initiator transaction and the Initiator
Request FIFO is already full, a retry will be issued to the AHB master that initiated the
request.
After gathering the appropriate information, the PCI Initiator interface performs the
specified transaction on the PCI bus, handling all bus protocol and any retry/disconnect
situations. The data will be moved from the South AHB to the PCI bus using the
Initiator Data FIFOs. The Initiator Data FIFOs are eight words deep.
supported PCI transaction types produced by the PCI Controller Initiator Interface of
the IXP45X/IXP46X network processors.
Table 190.

PCI Initiator Interface Supported Commands

PCI Byte Enables
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
It is important to note that the target interface — and the DMA channels used for
supporting the initiator interface — can contend for the use of the South AHB Master
Controller. When this contention occurs, arbitration for control of South AHB Master
Controller is carried out on two levels.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
phase Memory cycles are generated indirectly by AHB masters using a Non-
pre-fetch CSR mechanism. Refer to
page 501 for additional details.
Command Type
Interrupt Acknowledge
Special Cycle
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
"PCI Controller Configured as Host" on
I/O Read
I/O Write
(Reserved)
(Reserved)
(Reserved)
(Reserved)
® ®
Intel IXP45X and Intel
Table 190
Support
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Not supported
Supported
Not supported
IXP46X Product Line of Network Processors
Develepor's Manual
lists the
499