Intel IXP45X Developer's Manual page 510

Note that bits 23:20 are set to hexadecimal 3. For read accesses, byte-enables are
ignored. Bits 19:16 are set to hexadecimal 0, which denotes a read command. Bits
7:0 are set to hexadecimal 04.
2. PCI_CRP_RDATA is read by the AHB master that requested the PCI_SRCR to be
returned to the PCI_CRP_RDATA register.
When a write to the PCI Configuration Space is desired, the AHB master requesting the
write must update the PCI Configuration Port Write Data (PCI_CRP_WDATA) Register
with the data that is to be written to the PCI Configuration Register. Once the PCI
Configuration Port Write Data (PCI_CRP_WDATA) Register has been updated, a write
command is written into the command field of the PCI Configuration Port Address/
Command/Byte Enables (PCI_CRP_AD_CBE) Register along with the appropriate byte
enables and address of the PCI Configuration register to be accesses.
The data contained in the PCI Configuration Port Write Data (PCI_CRP_WDATA)
Register will be written to the PCI Configuration Register specified by the address and
byte enables contained in the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register. For Example:
1. An AHB master that wants to write a particular PCI Configuration Register writes
PCI_CRP_AD_CBE register first. Assume that the AHB master wants to write a
hexadecimal value of 0x00001234 to the Retry Timeout/TRDY Timeout
(PCI_RTOTTO) Register. The PCI_CRP_AD_CBE register is written with a
hexadecimal 0x00010040.
Note that bits 23:20 are set to hexadecimal 0. For write accesses byte enables are
active low. Bits 19:16 are set to hexadecimal 1, which denotes a write command.
Bits 7:0 are set to hexadecimal 40, which addresses the PCI_RTOTTO register.
2. Next, the hexadecimal value of 0x00001234 is written to the PCI Configuration
Register PCI_CRP_WDATA register, which causes the contents of the Retry
Timeout/TRDY Timeout (PCI_RTOTTO) Register to be written with a hexadecimal
value of 0x00001234.
One more example will demonstrate the effects of the byte-enables on write accesses
to the PCI Configuration Space:
1. Assume that the objective is to update the retry section of the Retry Timeout/TRDY
Timeout (PCI_RTOTTO) Register (Bits 15:8) without updating the TRDY terminal
count value of the Retry Timeout/TRDY Timeout (PCI_RTOTTO) Register (Bits 7:0).
The Retry Timeout/TRDY Timeout (PCI_RTOTTO) Register is located at hexadecimal
address 0x40. Also assume the value currently contained in the Retry Timeout/
TRDY Timeout (PCI_RTOTTO) Register is a hexadecimal 0x00008080.
2. The PCI_CRP_AD_CBE is written with hexadecimal 0x00D10040.
Note that bits 23:20 are set to hexadecimal D. For write accesses this allows only
byte 1 to be written (bits 15:8). Bits 19:16 are set to hexadecimal 1, which denotes
a write command. Bits 7:0 are set to hexadecimal 40, which addresses the
PCI_RTOTTO register.
3. Assume that the AHB master wants to write a hexadecimal value of 0x0000AB00 to
the second byte of the retry section of the Retry Timeout/TRDY Timeout
(PCI_RTOTTO) Register (Bits 15:8). The PCI_CRP_WDATA will be loaded with a
value of 0x0000AB00, which causes the contents of the retry section of the Retry
Timeout/TRDY Timeout (PCI_RTOTTO) Register (Bits 15:8) to be written with a
hexadecimal value of 0x0000AB00. The value that is now contained within the
Retry Timeout/TRDY Timeout (PCI_RTOTTO) Register is 0x0000AB80. Notice that
only one byte of data was manipulated.
Table 192
Configuration Space from within the IXP45X/IXP46X network processors) when using
the CRP access mechanism.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
510
®
Intel IXP45X and Intel
shows the PCI Byte Enables Byte Lane Mapping (accesses to the PCI
®
IXP46X Product Line of Network Processors—PCI Controller
August 2006
Order Number: 306262-004US