Intel IXP45X Developer's Manual page 890

Intel
Table 280. Slave Transactions
2
I C Slave
Action
Slave-receive
(default mode)
Setting the Slave
Address Detected
bit
Read one byte of
2
I C Data from the
IDBR
Transmit
Acknowledge to
master-
transmitter
Write one byte of
2
I C data to the
IDBR
Wait for
Acknowledge
from master-
receiver
Figure 201
relationships between master and slave devices.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
890
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
Mode of
Operation
• I
• The I
• I
Slave-receive
• If the first 8 bits are all zero's, this is a general call address. If the
only
• If the 8th bit of the first byte (R/W# bit) is low, the I
• Indicates the interface has detected an I
Slave-receive
Slave-transmit
• An interrupt is signalled (if enabled) after the matching slave
• Data receive mode of I
• Eight bits are read from the serial bus into the shift register. When a
• Occurs when the IDBR Receive Full bit in the ISR is set and the
Slave-receive
only
•
• As a slave-receiver, the I
Slave-receive
only
• The Ack/Nack Control bit controls the Ack data the I
• Data transmit mode of I
• Occurs when the IDBR Transmit Empty bit is set and the Transfer
Slave-transmit
only
• The IXP45X/IXP46X network processors will write a data byte to the
• As a slave-transmitter, the I
Slave-transmit
only
• See
through Figure 203 are examples of I
Definition
2
C Bus Interface Unit monitors all slave address transactions.
2
C Bus Interface Unit Enable bit must be set.
2
C Bus Interface Unit monitors bus for START conditions. When a
START is detected, the interface reads the first 8 bits and compares
the most significant 7 bits with the 7 bit I
and the General Call address (00H). If there is a match, the I
Interface Unit sends an Ack.
General Call Disable bit is clear, both the General Call Address
Detected bit and the Slave Address Detected bit in the ISR will be
set. See "General Call Address" on page
Unit stays in slave-receive mode and the Slave Address Detected bit
is cleared. If the R/W# bit is high, the I
transitions to slave-transmit mode and the Slave Address Detected
bit is set.
the IXP45X/IXP46X network processors (this includes general call
address). The IXP45X/IXP46X network processors can distinguish an
ISAR match from a General Call by reading the General Call Address
Detected bit.
address is received and acknowledged.
2
C slave operation.
full byte has been received and the Ack/Nack bit has completed, the
byte is transferred from the shift register to the IDBR.
Transfer Byte bit is clear. If enabled, the IDBR Receive Full Interrupt
is signalled to the .
CPU
will read 1 data byte from the IDBR. When the IDBR is read,
CPU
the IXP45X/IXP46X network processors will write the desired Ack/
Nack Control bit and set the Transfer Byte bit. This causes the I
Bus Interface Unit to stop inserting wait states and let the master
transmitter write the next piece of information.
2
C Bus Interface Unit is responsible for
pulling the SDA line low to generate the Ack pulse during the high
SCL period.
Unit drives. See "I2C Acknowledge" on page
2
C slave operation.
Byte bit is clear. If enabled, the IDBR Transmit Empty Interrupt is
signalled to the IXP45X/IXP46X network processors.
IDBR and set the Transfer Byte bit to initiate the transfer.
2
releasing the SDA line to allow the master-receiver to pull the line
low for the Ack.
"I2C Acknowledge" on page
2
C transactions. These show the
2
C Slave Address Register
891.
2
C Bus Interface
2
C Bus Interface Unit
2
C operation that addresses
2
C Bus Interface
883.
C Bus Interface Unit is responsible for
883.
August 2006
Order Number: 306262-004US
2
C Bus
2
C