Risc Super-Pipeline; Pipelines And Pipe Stages - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
3.10.2.1.2 Processor Pipeline Organization
The IXP45X/IXP46X network processors' single-issue super-pipeline consists of a main
execution pipeline, MAC pipeline, and a memory access pipeline. These are shown in
Figure 27, with the main execution pipeline shaded.
Figure 27.

RISC Super-Pipeline

Main Execution Pipeline
Table 96
Table 96.

Pipelines and Pipe Stages

Pipe / Pipe State
Main Execution Pipeline
Memory Pipeline
MAC Pipeline
MWB (not shown)
3.10.2.1.3 Out-of-Order Completion
Sequential consistency of instruction execution relates to two aspects: first, to the
order in which the instructions are completed; and second, to the order in which
memory is accessed due to load and store instructions. The IXP45X/IXP46X network
processors preserve a weak processor consistency because instructions may complete
out of order, provided that no data dependencies exist.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
F1 F2 ID
gives a brief description of each pipe-stage.
Handles data processing instructions
IF1/IF2 Instruction Fetch
ID Instruction Decode
RF Register File / Operand Shifter
X1 ALU Execute
X2 State Execute
XWB Write-back
Handles load/store instructions
D1/D2 Data Cache Access
DWB Data cache writeback
Handles all multiply instructions
M1-M5 Multiplier stages
MAC write-back - may occur during M2-M5
X1
RF
Mac Pipeline
M1 M2
Description
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Memory Pipeline
D1 D2 DWB
X2 XWB
Mx
B4354-01
Covered In
"Main Execution Pipeline" on
page 193
"
"
"
"
"
"
"Memory Pipeline" on page 194
"
"
"Multiply/Multiply Accumulate
(MAC) Pipeline" on page 195
"
"
Developer's Manual
191